Feature: RF and microwave


related energy into the DAC outputs, resulting in repeatable, phase- coherent spurs that degraded overall SFDR and compromised signal linearity. Tis observation established clock leakage as the dominant


limiting factor in the system’s spectral purity and guided the development of a targeted mitigation strategy combining hardware shielding, improved layout practices and algorithmic phase de- correlation to suppress these artefacts at their source.


Figure 2: Transmit characterisation plot showing combined channel performance across 6-14GHz


constrained by unwanted clock leakage within the DAC output spectrum; see Figure 2. Detailed spectral measurements indicated the presence of discrete spurious tones at harmonic offsets corresponding to the system clock frequency, suggesting a coherent coupling mechanism rather than random noise interference. Further investigation traced the root cause to radiative and


conductive coupling from the PLL ICs, which generated strong clock harmonics that inadvertently coupled into neighbouring DAC output traces. Te physical proximity of high frequency digital clock lines to sensitive analogue signal paths created an environment conducive to electromagnetic radiation and trace-to- trace crosstalk. Tese coupling effects effectively injected clock-


RF absorption wall installation To address the radiative coupling mechanism responsible for clock leakage into DAC outputs, RF absorption material was strategically installed around the heatsinks of the PLL ICs. Tis material functions as a lossy electromagnetic barrier, dissipating radiated clock energy as heat before it can couple into the adjacent sensitive analogue traces. Te goal of this modification was to suppress near- field radiation from high speed clock domains without altering the electrical characteristics of nearby transmission lines or disrupting thermal management. Following installation of the RF absorber material, the system


demonstrated a substantial improvement in spectral purity – even without any additional calibration or phase adjustment. Measured spur levels dropped by approximately 15dB, decreasing from -45dBm to -60dBm. Tis immediate improvement confirmed that a significant portion of the spurious energy was radiatively coupled and that absorption material alone could effectively attenuate these emissions. Building on the hardware based improvement, an additional


digital calibration was applied. Aſter the absorber material was installed (on a Quad-Apollo MxFE board without heatsinks), the PLL phase calibration script was executed to optimise clock phase relationships across devices. Tis algorithmic phase rotation yielded a further 20dB reduction in spur amplitude, achieving a total clock spur suppression of about 30dB and reaching a final spur level close to -75dBm. Te combined use of passive absorption and active phase de-correlation proved highly effective in minimising coherent clock feed-through. In implementing the absorptive shielding, careful attention was


paid to mechanical and electrical layout constraints. Absorption walls (Figure 3) were positioned to provide effective isolation around the PLL ICs whilst ensuring that the primary sample clock distribution paths remained unobstructed. Te absorber placement also preserved controlled impedance along critical PCB transmission lines (Figure 4), avoiding any adverse effects on signal integrity or clock distribution performance. Tis combination of targeted RF absorption and precise digital


calibration established a robust methodology for reducing radiative coupling and enhancing SFDR performance in dense, high-speed mixed-signal systems like the Quad-Apollo MxFE platform.


Figure 3: RF absorption material installation on heatsink around PLL touchdowns


System calibration with absorber Before phase rotation calibration, a system-level calibration was performed with absorbers installed. Tis step aimed to assess the baseline spur levels and output power, to determine if the absorber


38 April 2026 www.electronicsworld.co.uk


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