Feature: Automotive
insufficient for full verification.
• Hardware-in-the-loop (HIL): this is an option after hardware becomes available and is stable. This approach relies on existing hardware rather than a fully-instrumented verification testbench. As a result, verification stimulus is non-deterministic and observability may be limited, making debugging of issues extremely difficult. It may be useful for a quick checkout of newly-built integrated circuits, but it’s insufficient for thorough verification.
• Software simulation: this provides full-cycle accuracy prior to silicon availability, with excellent debug capabilities. It runs far too slowly for full verification of the SoC’s hardware and software. Booting an OS and testing software involves billions of execution cycles, much more than a simulator can manage in a reasonable timeframe.
• Hardware prototyping: whilst available before a chip has been manufactured, this approach lacks the capacity, debug visibility and design-change turnaround-time necessary for full- chip verification. Verification complexity is further
burdened by the high cost of silicon mask sets. Whilst the prior approaches applied before and after silicon availability may accomplish much of the checkout, any hardware bugs encountered can mean enormous delays and extra costs if a silicon re-spin becomes necessary. None of the traditional verification
approaches available before silicon are sufficient, due to several factors, such as lack of accuracy, limited debug, insufficient verification performance to deliver results in time for market,
Figure 1: Automotive SoCs are large and complex with multiple CPUs, AI capabilities and vision-oriented features, along with interfaces and protocols that need to be verifi ed
or being unable to provide the quality of results needed for such safety-critical applications. This leaves a pre-silicon verification gap. With these tools, it is not possible to do a complete verification job before generating the first silicon masks.
Emulation closes the gap Emulation is the only methodology available for thorough verification that can be executed fast enough to ensure production of a competitive SoC. Veloce emulators from Mentor, for example, provide not only full-chip verification, but also a connection to the higher-level suppliers that will integrate the SoC into systems and systems-of-systems. Silicon engineers who built SoCs in the
past will be familiar with emulation, but it may be a new tool for engineers who have previously designed limited automotive electronics. An emulator is a special-purpose supercomputer that models integrated
circuits before they’re built: • It can run 100-10,000 times faster than software simulation, because the models are implemented in hardware.
• It can handle as many as 15 billion logic gates.
• It is a full-on computing environment with its own computing hardware, operating system and software applications dedicated to simplifying specific verification tasks.
• Emulators can be housed in data centres, making them globally available through a networked connection.
• Emulators are new to the automotive industry, but they have proven their value in verifying complex SoCs for the telecommunications, storage and mobile markets for many years. They are a well- established verification tool. Because an emulator has such high
performance, it can run extensive test suites for both hardware and software. Its ability to test out software on hardware
Figure 2: Critical to success in the automotive realm is the full verifi cation that must be completed before chips are produced
www.electronicsworld.co.uk November/December 2020 47
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