Feature: Memory
The range of options for protecting data, and for locking the protection settings, is not necessarily well-known, even by long- standing users of NOR Flash memory devices
register bits are shown as BP0, BP1 and BP2. The three bits give eight options for selecting the size of the protected region, from as little as 1/64th of the array to as much as one half; see Table 1. So, the maximum granularity
available to the user is 1/64th of the total array. The problem is that today embedded systems require more storage than before, and Flash memory manufacturers have responded by providing products with larger memory capacity. The Winbond W25Q128JV, for instance, is a 128Mbit memory, of which 1/64th is 2Mbits. But what if the system designer only
needs to apply protection to boot code, and not to any other code or data, and the boot code is just 50kbits? In this case, a protected region of
2Mbits would store just 50kbits of code, and so – because the region has Program and Erase protection – most of the protected block will remain empty. Now, Winbond has introduced a new
feature to solve this problem: it is the ‘SEC’ status register bit shown at far left in Table 1. This SEC bit allows the designer to specify protection at the sector rather than the block level. As Table 2 shows, this divides the array into portions as small as 1/4096th – 32kbits in the W25Q128JV part, for instance. This gives the designer flexibility to protect very small pieces of critical code, such as boot code, whilst leaving the rest of the memory array free of Program/ Erase protection or available for storage of any other code and data. Table 2 also shows, highlighted in
yellow, another feature introduced by Winbond: the TB (top/bottom) register bit. By default TB = 0; the allocation of block or sector protection starts at the bottom of the array of addresses.
This is because most CPUs boot from the bottom of the array, so the protected region holding boot code should be at the bottom, for the fastest operation and the most efficient use of main memory. Intel CPUs, however, boot from the
top. So with the TB bit, Winbond gives users of Intel devices the option to allocate memory addresses at the top of the array for block or sector protection, by configuring TB = 1 in the status register.
Applying block protection entirely In standard NOR Flash memory ICs, the option to configure blocks for Program/Erase protection starts with the smallest 1/64th increment, and enables protection for up to half of the array, as shown in Table 2. In some applications, however, the requirement for storage of user data is nil or almost nil, and nearly all the memory array is occupied by boot and fixed application code. An example of such an application
is a TV remote control: there, only a small amount of unprotected memory
space is required for infrequent end-user configuration settings – for instance, to pair the remote control to a new media device. Nearly all the memory space is for application code, which will not change and so benefits from Program/Erase protection. A status register bit provided by
Winbond meets this application requirement. It is the Complement (CMP) bit: this reverses the protection setting asserted by the BP and SEC bits. If the BP bits are configured to protect a 1/64th portion of the memory array with the default setting of CMP = 0, when CMP = 1 protection will be applied to 63/64th portion of the array, and only 1/64th will remain unprotected.
Reinforced protection To provide additional confidence in the protection of critical data such as boot code, a NOR Flash memory IC can apply a hardware lock to the block/sector protection firmware (register) settings, achieved via the WP pin; see Figure 1. The status of the WP pin is controlled by the SRP (Status Register Protect) register bit. Some users might be familiar with
the WP pin in parallel Flash devices, where it has a simple Write Protect function. The function of the WP pin in serial NOR Flash devices is different: it protects the register settings that configure the Program/Erase protection of blocks and sectors via the BP and SEC register bits. Once the BP and SEC settings are made and the WP pin is
Table 1: The BPx bits in the status register of a NOR Flash device allow the user to specify the size of the protected region
44 November/December 2020
www.electronicsworld.co.uk
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