Column: JESD204 standard
Figure 5: Figure of /K/ character [K28.5], /R/ character [K28.0], /A/ character [K28.3], and /Q/ character [K28.4]
JESD204B transceiver block before 8B/10B coding, as would be seen on an FPGA logic analysis tool such as Xilinx ChipScope or Altera SignalTap.
• Symbol represents the hex value of the character that is to be transmitted, noting parity for PHY layer.
• Character is shown to indicate the JESD204B character as it is appears in the JEDEC specification.
The ILAS phase In the ILAS phase, there are four multiframes that allow the receiver to align lanes from all links and verify the link parameters. Alignment is required to accommodate trace-length differences and any character skew the receivers introduce. Each successive multiframe immediately follows the previous one of four; see Figure 4. Whether or not the scrambling link parameter is enabled, ILAS is always transmitted without scrambling. Te ILAS phase begins aſter SYNC~
has been deasserted (goes high). Aſter the transmit block has internally tracked (within the ADC) a full multiframe, it will begin to transmit four multiframes. Dummy samples are inserted between the required characters so that full multiframes are transmitted. Te four multiframes consist of the following: • Multiframe 1: begins with an /R/ character [K28.0] and ends with an /A/ character [K28.3].
• Multiframe 2: begins with an /R/ character followed by a /Q/ [K28.4] character, followed by link configuration parameters over 14 configuration octets (Table 1), and ends with an /A/ character.
• Multiframes 3 and 4: the same as Multiframe 1. Te frame length can be calculated for
the JESD204B parameters: (S) × (1/Sample Rate).
18 April 2019
www.electronicsworld.co.uk Table 1: Fourteen JESD204B configuration parameters octets in ILAS Multiframe 2
Data phase with character replacement enabled In the data transmission phase, frame alignment is monitored with control characters. Character replacement is used at the end of frames. Tere is no additional overhead needed to accommodate data or frame alignment during the data phase. Character replacement allows an alignment character to be issued at a frame boundary if and only the last character of the current frame can be replaced with the last character of the last frame, facilitating (occasional) confirmation that the alignment has not changed since the ILAS sequence. Character replacement in the transmitter
occurs in the following instances: • If scrambling is disabled and the last octet of the frame or multiframe equals the octet value of the previous frame.
• If scrambling is enabled and the last octet of the multiframe is equal to 0x7C, or the last octet of a frame is equal to 0xFC. Transmitters and receivers each maintain a local multiframe counter (LMFC) that
perpetually counts to (F × K) − 1 and then wraps back to “0” to count again (ignoring internal word width). A common (sourced) SYSREF is issued to all transmitters and receivers that use the SYSREF to reset their LMFCs, aſter which all LMFCs should be synchronised (within one clock cycle) to each other. At the release of SYNC (seen by all devices)
the transmitter begins ILAS at the next (Tx) LMFC wrap to “0.” If F × K has been properly set to be greater than the (transmit encode time) + (line propagation time) + (receiver decode time), received data will propagate out of the receiver’s SERDES before the next LMFC. Te receiver will pass the data into a FIFO, which will begin outputting data at the next (Rx) LMFC boundary. Tis known relationship between the transmitter’s SERDES input and the receiver’s FIFO output is known as “deterministic latency”.
Te second part of this article will appear in the next issue
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