Column: JESD204 standard


Working with the JESD204B interface


By Anthony Desimone and Michael Giancioppo, Applications Engineers, Analog Devices


J


ESD204B is a JEDEC- approved standard for serial data interfacing between converters and digital processing devices. As a third-generation standard,


it addresses some limitations of the earlier versions. Benefits include reductions in required board area for data interface routing, which in turn results in smaller packages for converter and logic devices, and reductions in setup and hold times. Although the JESD204B standard is


documented by JEDEC, some specific information about it is subject to interpretation or may be spread over multiple references.


JESD204B synchronisation Te JESD204B method links one or more ADCs or DACs to an FPGA, for example,


over a higher-speed serial interface compared to the more typical method of parallel data transfer. Te interface, which runs at up to 12.5Gbps/lane, uses a framed serial data link with embedded clock and alignment characters. It eases the implementation of the data interface of high-speed converters by reducing the number of traces between devices, thus reducing trace-matching requirements, and eliminating setup- and hold-timing constraint issues. Since a link needs to be established prior to data transfer, there are new challenges and techniques required to identify that the interface is working properly and, if not, how to fix it. Te JESD204B interface uses three


phases to establish the synchronised link: code group synchronisation (CGS), initial lane synchronisation (ILAS) and data transmission phase. Te required signals


Figure 1: JESD204B link diagram for one ADC to an FPGA through one lane


Figure 2: Logic output of JESD204B subclass 0 link signals during CGS phase; assumes two lanes, one device with two ADCs


16 April 2021 www.electronicsworld.co.uk


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