Column: JESD204 standard


Figure 3: Logic output of /K28.5/ characters and how it propagates through the JESD204B Tx signal path


for the link are a shared reference clock (device clock), at least one differential CML physical data electrical connection, called a lane, and at least one other synchronisation signal (SYNC~ and possibly SYSREF). Te signals used depend on the subclass: • Subclass 0 uses device clock, lanes and SYNC~.


• Subclass 1 uses device clock, lanes, SYNC~ and SYSREF.


• Subclass 2 uses device clock, lanes and SYNC~. Subclass 0 is adequate in many cases and


will be the focus of this article. Subclasses 1 and 2 provide a method to establish deterministic latency. Tis is important in applications where synchronising multiple devices, or system synchronisation or fixed latency is required (for example when a system needs a known sampling edge for an event, or an event must react to an input signal within a specified time). Figure 1 shows a simplified JESD204B


link from the transmit device (an ADC) to the receive device (an FPGA), with data from one ADC using one lane. Although there are many variables


within the JESD204B specification, some have particular importance when establishing a link. Tese key variables are (note that these values are typically represented as “X − 1”): • M: number of converters. • L: number of physical lanes. • F: number of octets per frame. • K: number of frames per multiframe. • N and N’: converter resolution and number of bits used per sample (multiples of 4), respectively. N’ value is N value, plus control and dummy bits.


Subclass 0: synchronisation steps Many applications can use the relatively simpler Subclass 0 mode of operation – the easiest mode to establish and verify a link for. Subclass 0 uses three phases to establish


and monitor synchronisation: CGS phase, ILAS phase and data phase. Te figures associated with each phase present the data in different formats, as they might be seen on an oscilloscope, logic analyser, or FPGA virtual I/O analyser.


The code group synchronisation (CGS) phase Te most significant parts of the CGS phase that can be observed over the link are shown in Figure 2, along with a description of the highlighted points in the figure. • Te receiver issues a synchronisation request by driving the SYNC~ pin low.


• Te transceiver transmits /K28.5/ symbols (10 bits/symbol), unscrambled beginning the next symbol.


• Te receiver synchronises when it receives at least four consecutive/K28.5/symbols without error; it then drives the SYNC~ pin high.


• Te receiver must receive at least four 8B/10B characters without error, otherwise


synchronisation fails and the link stays in CGS phase.


• CGS phase ends and ILAS phase begins. Te /K28.5/ character, also just known as


/K/, within the JESD204B standard can be exhibited as shown in Figure 3. Te standard requires a running neutral disparity. Te 8B/10B coding allows a balanced sequence that, on average, contains an equal number of ones and zeroes. Each 8B/10B character can have a positive (more 1s) or negative (more 0s) disparity, and the parity of the current character is determined by the current sum of the previous characters sent. Tis is typically accomplished by alternately transmitting a positive parity word and a negative parity word; the figure shows both polarities of the /K28.5/ symbol.


Note these key points: • Serial value represents the logic levels of the 10 bits transmitted over the lane, as would be seen by an oscilloscope measuring the physical interface.


• 8B/10B value represents the logic values (10 bits) transmitted over the lane, as might be seen by a logic analyser measuring the physical interface.


• Data value and data logic represent the logic levels of the symbol inside the


Figure 4: Logic output of JESD204B subclass 0 link signals during ILAS


www.electronicsworld.co.uk April 2021 17


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