EDA
Automating processor design: How to avoid the trade-off between fl exibility and performance
By Mike Eftimakis, VP strategy & ecosystem, Codasip R
ISC-V is the open-source Instruction Set Architecture (ISA) that is gaining signifi cant popularity in an increasingly diverse set of applications. This
is all down to RISC-V’s fl exibility, scalability, and modularity. By now, I am not sure RISC-V needs much of introduction.
The fact is, RISC-V enables a ‘freedom of design across all domains and industries’ in the words of RISC-V International which is the non-profi t home of the open standard RISC-V ISA, related specifi cations, and stakeholder community. There are more than 2,700 RISC-V members across 70 countries.
One of the main reasons RISC-V is growing so quickly is the potential of the ISA to tailor both the instruction set and microarchitecture of the processor to meet specifi c application requirements. This capability leads to custom compute solutions, enabling developers to create hardware that is optimized for their workloads.
Engineers who design systems inevitably are forced to make trade-offs between fl exibility and performance. The most fl exible approach is to choose a general-purpose core and to only optimise the software to suit the system requirements. This straightforward approach works for any fi xed “off-the-shelf” processor. It has limits in terms of system performance: algorithms are often executed ineffi ciently to overcome inherent mismatch in the system, and therefore everything runs slowly. The usual way around this performance problem is to create fi xed-function circuits. These are designed to perform a specifi c set of operations. These hardware functions can be extremely fast, but hard coding anything means it is diffi cult if not impossible to modify or update later. This restricts the ability to meet changing application needs. The best solution is to combine these approaches: maintain the fl exibility of the software but bring additional logic into the processor to enable faster operation.
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down, custom compute delivers gains in power-performance and area that can no longer be achieved by simple shifts in process. Applications requiring high performance, low latency, or high energy effi ciency, are particularly suited to a custom compute approach.
Effi ciency improvements of RISC-V custom instructions. Source: Codasip
RISC-V offers a level of customisation that means designers can create custom instructions tailored to the needs of their own application. Custom instructions can be used to accelerate critical operations, reduce memory access, and improve energy effi ciency. As an example, a custom instruction with a specifi c AI algorithm can reduce the number of clock cycles needed to perform the operation. One example from Codasip is: Embedded AI on L31 – compact neural network accelerator in CodAL. In this paper, engineers examined what could make it easier to run AI algorithms on resource-constrained embedded devices – both from a software and a hardware point of view.
When hardware and software teams do collaborate, and select the optimum custom instructions, the result can be a step up in the effi ciency of the overall implementation. However, if these teams are to work closely together, it requires a change in habits and a new methodology.
In order to reap the benefi ts of processor
customisation, hardware and software architects need to collaborate from the beginning of the product development, running software algorithms to reveal gains that would be impossible to achieve if the hardware was already frozen.
Codasip supports such a collaboration with a common language (CodAL) and tools to run software even before hardware designers start integrating the SoC.
Processor effi ciency can be improved effectively by adding certain custom instructions. But these instructions can fall short of really tailoring the processor to the target system or application. Modifi cations that go beyond just adding instructions can bring benefi ts tailored to the application.
For example, architects may want to increase the data throughput between the processor and interfaces or other processing elements, parallelize operations, manage certain data types, or add application-related features. Codasip calls this custom compute – a methodology which makes it possible to optimize hardware for the expected workload of the application. With Moore’s law slowing
The benefi ts of co-optimi- sation of the software and hardware. Source: Codasip
Most designers will use a custom compute approach to achieve performance and energy effi ciency for their target applications. But embedding security features into the processor, and adding custom instructions, can also improve the overall security of a system. The custom element makes life diffi cult for potential attackers.
When it comes to industrial or automotive applications, improved reliability and easy maintenance are two of the most fundamental requirements. Using custom compute, the system designer can add error-correcting features and runtime hardware checks to minimise system downtime and ultimately reduce the risk of hardware failure. This design approach is particularly suitable to Industrial IoT (IIoT) applications.
RISC-V custom instructions offer important effi ciency improvements. A closer collaboration between hardware and software design teams makes possible an approach of custom compute. That teamwork needs to be supported by a strong methodology and by effi cient design automation tools capable of simplifying an otherwise enormous task. RISC-V IP is primed for customization, with the ability to tailor the processor perfectly to your own application. The right processor and processor design automation tools, such as Codasip Studio tool for its RISC-V processor IP, will help designers identify areas for improvement and support an effective hardware / software co-optimization methodology.
https://codasip.com/ Components in Electronics
www.cieonline.co.uk.uk
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