FEATURE EMBEDDED TECHNOLOGY
A logical solution for developing machine vision systems
Giles Peckham, regional marketing director at Xilinx and Adam Taylor CEng FIET, embedded systems consultant take a closer look at developing machine vision applications using Xilinx All Programmable Zynq SoC or Zynq UltraScale+ MPSoC devices and the company’s reVISION acceleration stack
E
mbedded Vision systems or machine vision systems are ubiquitous across
the industrial landscape, performing a range of applications from manufacturing line optical inspection to postal sorting. The traditional approach has been to develop machine vision systems around a PC based architecture, benefiting from ease of deployment, the large ecosystem of software vendors and the low cost of implementation. In some cases GPU acceleration is also used within the PC architecture forming a PC/GPU architecture. However, with both PC and PC/GPU based approaches it is difficult to implement a scalable, responsive and power efficient solution which enables processing at the edge, while providing the range of interfacing capabilities required.
To address these challenges, machine
vision developers can utilise the Xilinx All Programmable Zynq SoC or Zynq UltraScale+ MPSoC devices and develop applications using the reVISION acceleration stack. These devices provide programmable logic coupled with high performance ARM A53 or A9 processors, forming a tightly integrated heterogeneous processing system. The inherent parallel nature of the programmable logic can be leveraged to accelerate the image processing pipelines and machine learning inference engines, while the processing system implements higher-level decision making, communication and system management functions. When combined, this enables the creation of a more responsive, power efficient solution. When it comes to interfacing, both the All Programmable Zynq SoC and Zynq UltraScale+ MPSoC provide a range of industry-standard interfaces which can be provided via the processing system or the programmable logic. Legacy or bespoke interface functionality can be implemented using the programmable logic thanks to the flexibility of the IO structures, requiring only an external PHY to achieve the physical layer of the protocol providing any-to-any connectivity.
28 MAY 2018 | ELECTRONICS
2. Algorithm Development – This layer provides support for acceleration of both OpenCV image processing and Caffe machine learning inference functions into the programmable logic.
Figure 1:
reVISION Acceleration Stack
Figure 2:
Improved latency, determinism and power dissipation using Programmable Logic
The reVISION acceleration stack enables developers to target these All Programmable devices using OpenCV, OpenVX and Caffe, which are industry- standard libraries and frameworks for the development of machine vision and machine learning applications. To enable more responsive solutions, reVISION can accelerate several OpenCV functions including the OpenVX core functions into the programmable logic. It is also possible to accelerate machine learning inference engine layers including Conv, ReLU, Pooling and Detector and Classifier into the programmable logic. The reVISION stack consists of three
Figure 3 - Development time reduction using reVISION and SDSoC
distinct layers, providing all the necessary elements to implement the algorithms required for machine vision: 1. Platform Development – This layer provides the hardware and software platform definition for the SDSoC tool.
3. Application Development – The highest layer of the stack provides support for industry standard frameworks such as Caffe and OpenVX. Combining reVISION with All Programmable Zynq SoC or Zynq UltraScale+ MPSoC devices has shown in benchmark tests a significant performance increase, demonstrating up to 42x frames per second per watt increase for image processing or up to six times images per second per watt increase for machine vision applications, compared with GPUs. Developing using reVISION also brings
with it significant reductions in the development time when compared with a traditional RTL based development. This development flow would present a gap between the high-level embedded vision and machine learning algorithms and the RTL design implemented within the programmable logic, which would require the high-level algorithms to be recreated in RTL, increasing development time and cost. reVISION and SDSoC remove this gap, enabling the developers to focus upon creating their value-added activity, achieving a faster time to market with a lower development cost.
THE CHALLENGES AHEAD Machine vision applications are facing several challenges requiring power efficient, responsive and scalable solutions capable of processing at the edge and interfacing with a wide range of industry standard, bespoke and legacy interfaces. The flexibility and capability provided by All Programmable Zynq SoC or Zynq UltraScale+ MPSoC devices combined with the reVISION stack, enable machine vision developers to address these challenges.
Xilinx
www.xilinx.com T: (0) 1932 574600
/ ELECTRONICS
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