NANOTECHNOLOGY
Advancing the chip’s back-end-of-line
Swati Achra, currently undertaking a PhD in materials engineering in MTM department, and part of the Nano-interconnects team at imec KU Leuven, explores the promise of hybrid graphene/metal structures for advanced interconnects
W
hile chipmakers continue to make advancements with transistor technologies in the front-end-of-line (FEOL), the
interconnects within the chip’s back-end-of-line (BEOL) are challenged to keep pace. This BEOL is organised in different metal layers (local, intermediate, semi-global and global) which are vertically interconnected by means of via structures – filled with metals. With each new technology generation, routing congestion and a dramatic signal delay (resulting from an increased resistance-capacitance (RC) product) become more and more problematic, forcing chipmakers to consider new integration schemes and materials for fabricating the interconnects. For the 5nm technology node – the most advanced chip
generation that has entered volume production – critical local interconnects have metal pitches as tight as 28nm. Cu-based dual damascene still is the workhorse process flow for making the interconnects. But with metal pitches soon moving towards 21nm
and beyond, chipmakers may gradually move away from mainstream technologies. Imec, for example, foresees the introduction of alternative integration schemes such as hybrid via metallisation, a semi-damascene process and hybrid height with zero via for the nodes to come. In parallel, alternative conductors with better figure of merit are
being investigated to be used in combination with these advanced process schemes. This figure of merit is defined as the product of the bulk resistivity and the mean free path of the carriers in the metal. Of interest are cobalt (Co), ruthenium (Ru), tungsten (W) and ordered binary intermetallic compounds such as AlNi or RuV3. In addition, researchers look intensely at graphene, which, thanks
to its remarkable properties, is making its way into many interesting fields of application such as (bio)sensing, energy storage, photovoltaics, opto-electronics and CMOS scaling.
Figure 1: A view on the imec FEOL (top) and BEOL (bottom) technology roadmaps 40 JUNE 2021 | ELECTRONICS TODAY
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50
