FEATURE EDA
HOW TO REDUCE SYSTEM- LEVEL DESIGN EFFORT
John Park, product management director, PCB & IC package group at Cadence explores ways to reduce system-level design effort by integrating the IC, package and system design environments
M
any of today’s analogue, RF and mixed-signal designs require the
integration of multiple ICs across varying substrate technologies to achieve required performance goals. Given the complexity of today’s chips, packages and boards, ICs based on both silicon and non-silicon materials are now required to design optimal high- performance systems. The integration of heterogeneous devices allows designers to achieve results that can’t easily be duplicated using a monolithic IC (SoC) design approach. However, heterogeneous integration introduces a whole new set of challenges for designers. Today, designing at the “system level”
(IC-package-PCB) involves a lot of educated guesswork regarding the downstream effects of the package/PCB on the performance and reliability of the chip(s). Traditionally, the analogue/RF IC designer would only simulate standalone ICs without considering the effects of the package and PCB. The package contains single, or multiple ICs and interconnects. In addition, it probably contains discrete components required by the ICs to function. Similarly, the PCB contains several packages, interconnects and discrete components. It is important to simulate the entire system together to capture the performance at high frequencies. Because the IC designer and the package designer use different schematic entry tools, the IC designer must re-capture the package system schematic as a testbench around the IC schematic to do combined system simulations. To identify and eliminate such errors at an early design stage and long before tapeout, it is essential to have a familiar design and simulation environment that auto-enables the IC designer to simulate the IC in context of the entire PCB, package system and parasitics. While such an environment exists for simulating I/O to I/O interconnects for digital ICs, the Cadence Virtuoso System Design Platform allows simulation of the analogue/RF IC in context of a complete PCB/package circuit inclusive of parasitics and minimises design iterations. The implementation flow provides the
20 FEBRUARY 2018 | ELECTRONICS
propagates edits in the schematic to SiP Layout and conversely. Designers can also generate a BOM, visualise design differences in an intuitive manner and look at layout reports using this flow. Once the package or PCB is designed
Figure 1:
Virtuoso system design platform
capability to drive IC and package layout through a single schematic editor. By having the same schematic editor (Virtuoso Schematic Editor), the IC designer is in a much better position to do system-level design in a common environment with pre-layout system simulations (IC and package together) and then drive the layout of the respective domain. This flow also automates much of the package-level library development process by generating die footprints to be used in Cadence SiP Layout.
CO-DESIGN BETWEEN DIE AND PACKAGE
Figure 2: RS Pro Evikey
Advanced users can co-design between the die and the package to achieve better package-level routing and/or wire bonding. The implementation flow allows the designer to design schematics of packages in the Virtuoso Schematic Editor before pushing it to a package layout editor. It further allows the designer to export die footprints and symbols from the Virtuoso Layout Suite and use them to construct a package schematic. The bidirectional flow of data dynamically
using the implementation flow described here, the analysis-based flow brings in the complete simulation environment, requiring minimal knowledge in PCB or package and electromagnetic simulation domains. This approach will result in a significant improvement in productivity. The analysis flow allows the IC designer to import a PCB and package layout with its corresponding parasitic models, represented by S-parameters or SPICE, to the IC design environment. The flow reads the PCB or package connectivity and creates a schematic with parasitic models stitched in. The schematic becomes ready to simulate in context of the PCB or package system. This design platform helps to integrate and simulate the IC in context of all such package/PCB interconnects and external components. This assumes greater importance because the IC, package and PCB are typically designed by different teams using different design tools across geographic locations, all independent of the others and at different stages of the design cycle. This platform brings the package and PCB-level layout parasitics into a common schematic, enabling cross- domain simulation of the complete system. This helps identify critical performance deviations before tapeout. Communication of required modifications can then be driven directly to package/ PCB teams. An important feature here is to intelligently stitch the parasitic models into the simulation schematic. If the models also contain discrete devices, they should be auto-filtered when the simulation schematic is created so that they are not double- counted in the simulation. The auto-filtering requires re-adjustment of the interfaces to ensure proper stitching and removal of all such SMDs to avoid redundancy.
Cadence
www.cadence.com T: 01344 360333
/ ELECTRONICS
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