TEST & MEASUREMENT
Challenges and Solutions for Testing AI Semiconductors
By Martin Dresler, senior director of business development, V93000 Performance Digital, Advantest
I
n recent years, the semiconductor industry has witnessed a rapid growth in demand intelligence (AI) and machine learning (ML) applications. This includes high-performance computing (HPC) chips, such as graphics processing units (GPUs), which are essential components of the data centers that power large language models (LLMs). With AI-enabled smartphones and personal computers starting to ramp up now, the market for AI devices is expected to grow exponentially in the coming years. As this technology grows more and more complex, it creates a demand for advanced test solutions to enable its development.
AI chip characteristics and challenges
The high-performance semiconductors used to power AI applications are incredibly complex. The modern AI GPU contains several hundred billion transistors and utilizes advanced processing nodes with multiple cores running various workloads at once. Although some manufacturers make general-purpose GPUs, many chips used for AI are custom-made to support the needs of circuits (ASICs) are incredibly complex and require highly specialised test solutions to ensure performance and reliability. AI chips have high power demands and thermal requirements, posing complex test challenges related to power delivery. Some devices are already drawing over 1,500 A, with future plans for 2,500 A and more, so controllability of the power resources is critical, requiring precise regulation, fast clamping capability and in-line monitoring of contact resistance. Moreover, the high transistor density of ASICs coupled with high power delivery can lead to hotspots that can potentially damage device structure. AI chips thus require advanced test equipment with extreme precision to test multiple cores in parallel while mitigating thermal risk. Increasingly, testers must have sophisticated thermal management capabilities that enable engineers to minimise hot spots and
36 MARCH 2025 | ELECTRONICS FOR ENGINEERS
monitor thermal conditions.
The trend toward advanced packaging also presents various challenges for test. Stacking multiple ICs and dynamic
random-access memory (DRAM) modules on top of each other to achieve higher processing speeds enables less power consumption and smaller footprints but can be risky; if one device fails, the entire multi-die cost to the manufacturer. To mitigate this risk, test must “shift left” or occur earlier in the manufacturing process. Most testing is performed at the wafer level, but as these devices grow more complex, we are seeing rising demand for die-level test, testing individual die after they have been diced, with superior thermal capabilities. Employing die-level, or “Known Good Die” (KGD), test processes allows manufacturers to remove defective components before packaging, ensuring functionality and reliability. In addition to necessitating more testing earlier in the manufacturing process, the growing complexity of AI devices also requires testing at later stages in the testing a semiconductor’s operations in the functionality of the device as a whole, testing the performance of all the integrated components within the device under real-world conditions. Once considered an optional step, SLT enables engineers to identify complex issues in system operation that may not have been detected earlier in the test
process to ensure quality and reliability. Although AI devices pose complex test challenges, many test engineers are utilising AI to improve the testing process. ML tools analyse data in real time, identifying not only failing or marginal chips, but also those whose data indicates potential failure in later testing stages. This helps reduce test time and improve the reliability and quality of the end product.
Integrated Solutions
Advantest is addressing these challenges with its integrated, comprehensive portfolio of test platforms designed for high-quality, cost-effective testing at high throughput. This includes the V93000 SoC test system, which range of test methods and applications. Advantest also offers V93000-optimised equipment and services, such as die-level handlers, test interface boards, custom-engineered sockets, advanced thermal control units, system-level test systems, memory test systems and advanced data analytics, to support testing high-performance AI-capable devices.
Conclusion
As we step into the AI-driven future, the rise of complex, high-performance devices will continue to drive demand for semiconductor tests. Widespread industry collaboration and cutting-edge, integrated test solutions are needed to address these complexities and drive innovation.
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