Signal conditioning And then solving this last equation for the minimum


required GBP given a target F-3dB, Rf, and Cs will give this constraint.


increase the overall TIA gain from Rf + R2 up to Rf × At + R2. Looking first at the DC gain and offset effects of adding R1 and R2 and targeting a total TIA gain of Zt.


1. Sweeping across different R1 and R2 solutions, usually using relatively low resistor


Clearly, for a given source capacitance, the


GBP, Rf, and F-3dB are tightly coupled. For a given GBP and Cs, achieving more gain will reduce the bandwidth or, conversely, needing


more bandwidth will require reducing the Rf value (gain).


HOW ADDING A RESISTIVE TEE NETWORK TO A TIA DESIGN HELPS The example of Figure 1 is asking for a relatively low 0.42pF feedback capacitor. Typical surface-


mount device (SMD) resistors used for Rf will have 0.18pF to 0.2pF parasitic, so the actual


physical external Cf needs to be reduced to 0.22pF. While that might be achievable, using a small amount of in-circuit tee gain can shift


that required Cf value up into a much more repeatable region - or, when the required Cf is <0.20pF, can shift it up to that parasitic value with


some amount of tee gain inside the loop. Figure 4 shows the starting point for a TIA design using a feedback tee inside the feedback loop.


Leaving R1 out of the circuit for now, increasing R2 from 0 will add R2 to Rf in the TIA gain. For instance, setting R2 = 1kΩ will increase the TIA gain to 21kΩ in Figure 4. As the R1 element is also brought into play, that 1 + R2/R1 = At gain on the voltage at the output of Rf will


values to keep their noise out of the total integrated output noise expression, try to hold


the sum of R1 + R2 = Rl at some target op amp load - usually that will be the load used for the Aol curve generation.


2. As the At gain is ramped up from 1


(no R1 in the circuit), the required Rf value will ramp down as Rf = Zt – R2 /At.


3. Given an Rl and Zt, solving for R2


and R1 as At is ramped up from 1 gives the following:


A. R2 = Rl × (At – 1)/At B. R1 = Rl/At


4. To retain input bias current error


cancellation as Rf is being reduced (for a bipolar input op amp solution), reduce Rbal to equal the new Rf value. This cancels the error voltage at the output of the Rf element due to matched input bias current terms in


most bipolar input op amps. There will still be an input offset voltage error that will get an increasing gain to the output by the At gain. Where the input bias currents are relatively large (as in this bipolar input LT6200-10), reducing these Rbal = Rf values also reduces


Adding a tee network has increased the


required Cf for any target design while also reducing the required Rbal value in bipolar input solutions, reducing the input CM voltage shift due


to input bias currents. It has also increased the gain for the op amp’s input offset voltage by that tee gain over the simple TIA design and slightly increased the output integrated noise. Normally, this approach would use modest


levels of tee gain to get the Cf value at or above parasitic levels. Simply selecting a desired tee gain would proceed as follows:


1. Choose an At value


2. With a target R2 + R1 loading set as Rl, solve for R2 = Rl × (At – 1)/At


3. Then R1 = Rl/At


4. Reduce the Rf value to get the desired Zt gain using Rf = (Zt – R2)/At


the input CM voltage shift due to Ib+ into Rbal. This can be very useful in higher targeted TIA gains (Zt) to keep the input CM voltage in range. JFET or CMOS input op


amp solutions would not use an Rbal element as their input bias currents are much lower and not normally matched.


5. For compensation, it will turn out that


the feedback pole (P1) location set by a now reduced Rf value will stay constant - forcing the Cf value up. This can be very useful to increase Cf into a more realisable range.


Figure 4. Example design using a feedback tee network with R2 and R1. 60 March 2026 Instrumentation Monthly


Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44  |  Page 45  |  Page 46  |  Page 47  |  Page 48  |  Page 49  |  Page 50  |  Page 51  |  Page 52  |  Page 53  |  Page 54  |  Page 55  |  Page 56  |  Page 57  |  Page 58  |  Page 59  |  Page 60  |  Page 61  |  Page 62  |  Page 63  |  Page 64  |  Page 65  |  Page 66  |  Page 67  |  Page 68  |  Page 69  |  Page 70  |  Page 71  |  Page 72