Test & measurement
resistance of around 500 mΩ between the LTC2063’s inputs and RSENSE. The main source of uncertainty in the output of this circuit is noise, so
filtering with large parallel capacitors is crucial to reduce noise bandwidth and thus the total integrated noise. With a 1.5 Hz output filter, the LTC2063 adds about 2 µV p-p low frequency, input-referred noise. Averaging the output over the longest possible duration further reduces error due to noise. Other sources of error in this current sense circuit are parasitic board
resistance in series with the RSENSE at the LTC2063 input, tolerance in resistance values of the gain-setting resistors RIN and ROUT, mismatched temperature coefficients in the gain-setting resistors, and error voltage at
the op amp inputs due to parasitic thermocouples. The first three sources of error can be minimised by using Kelvin sense, 4-lead sense resistors for
RSENSE, and using 0.1 per cent resistance with similar or low temperature coefficients for the critical gain-set path of RIN and ROUT. To cancel out the parasitic thermocouples at the op amp inputs, R1 should have the same
Figure 2. No plateau at the low end, down to 100 µA ISENSE. Another source of zero-point error is the output PMOS’s zero-gate
voltage drain current, or IDSS, a parasitic current that is present for nonzero VDS when the PMOS is nominally turned off (|VGS| = 0). A MOSFET with high IDSS leakage will produce a nonzero positive VOUT with no ISENSE. The transistor used in this design, Infineon’s BSP322P, has an upper-bound
IDSS of 1 µA at |VDS| = 100 V. As a good estimate for the typical IDSS of the BSP322P in this application, at room temperature, with VDS = –7.6 V, IDSS is only 0.2 nA, resulting in just 1 µV error output, or equivalent 100 nA input current error, when measuring 0 A input current.
Architecture The LT1389-4.096 reference, along with the bootstrap circuit composed of M2, R2, and D1, establishes a very low power isolated 3 V rail (4.096 V +
VTH of M2, typically –1 V) that protects the LTC2063 from seeing its absolute maximum supply voltage of 5.5 V. Although a series resistance could suffice for establishing bias current, using transistor M2 allows for much higher overall supply voltages while also limiting current consumption to a mere 280 µA at the high end of the supply range.
Precision
The LTC2063’s input offset voltage contributes a fixed input-referred current error of 10 µA typical. Out of 250 mA full-scale input, the offset results in only 0.004 per cent error. At the low end, 10 µA out of 100 µA is 10 per cent error. Since the offset is constant, it can be calibrated out. Figure 3 shows that total offset from LTC2063, unmatched parasitic thermocouples, and any parasitic series input resistances is only 2 µV.
metal terminals as RIN. Asymmetric thermal gradients should also be avoided as much as possible at the inputs.
The overall contribution of all the error sources discussed in this section is at most 1.4 per cent when referenced against full-scale 2.5 V output, as shown in Figure 4.
Continued on page 46...
Figure 3. VIN to VOUT conversion on minimum supply 4.5 V for the entire ISENSE
range. An output offset of 200.7 μV, when divided by 100.05 V/V voltage gain, implies an RTI input offset of 2 μV.
The gain shown in Figure 3, 100.05 V/V is 1.28 V/V greater than the
expected gain given by the actual values of ROUT and RIN when built, or 4.978 kΩ/50.4 Ω = 98.77 V/V. This error may be due to parasitic series
Instrumentation Monthly August 2020 45
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