Data acquisition
Figure 2. Phases of the AD4696 with high-Z enabled and disabled.
WHAT IS INPUT HIGH-Z TECHNOLOGY? The term high-Z technology, in the context of analogue input, refers to a collection of circuit techniques that - without consuming static or continuous power - substantially increase the effective input impedance of the ADC. This makes the input of the ADC easy to drive. Let us assume that the muxed ADC is
converting on Channel N – 1 and that the next channel to be converted is Channel N. At the rising edge of convert start (CNV), the channel voltage is sampled. In Figure 2, the first rising edge of CNV samples the voltage on Channel N – 1. The ADC then converts the sampled voltage on Channel N – 1. After the conversion, with the input high-Z disabled, the ADC proceeds to acquire the next channel in the sequence, which is Channel N. The voltage on Channel N can often be substantially different from the voltage on Channel N – 1, to which the ADC capacitor is now charged. This results in a huge voltage kick on Channel N (dark blue dashed line) and introduces a large error in the channel voltage at the sampling instant (second rising edge of CNV). This necessitates a large external capacitor to absorb the kick and a driver amplifier to supply the necessary charge. When the input high-Z is enabled, the
internal sampling capacitor of the ADC is charged up to the present voltage on the channel it is going to acquire before it begins the real acquisition. Immediately following the conversion on Channel N – 1, a high-Z phase is introduced that accurately charges the ADC sampling capacitor to the present voltage on Channel N. This means that when the ADC sampling capacitor does connect to the
Instrumentation Monthly September 2022
external input, it does not source any charge and does not result in any kickback. In practice, there is usually a small residual error due to the charge injection of the internal switches (first charge kick). This small residual error results in practically negligible settling error at the sampling instant of Channel N. This charge error with the high-Z enabled would enable a massive improvement in the settling dynamics of the system.
When the sampling on Channel N is done,
the ADC must proceed to do the conversion. So, the internal switches disconnect the ADC sampling capacitor from the external input. This results in a second charge kick due to the switch opening charge injection. Typically, the
second charge kick has longer time to settle, so the magnitude of the first charge kick determines the settling error on a channel. Therefore, the first charge kick magnitude must be minimised.
The input high-Z technology is incorporated
in the AD4696 (latest generation muxed SAR ADC) as part of the EasyDrive feature set. As a result, the AD4696 begins acquisition on a channel extremely smoothly. It eliminates the need for a kickback absorption capacitor and a driver amplifier for each channel. This results in the massive reduction of the system footprint and power consumption, as well as a significant simplification of the signal chain, as shown in Figure 3.
Figure 3. A signal chain with the AD4696 muxed SAR ADC.
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