Feature sponsored by Test & measurement
USB 3.2 DEVICE ERROR EXAMPLE Fig. 3 shows an example of errors that occurred during the transmitted eye test for a USB 3.2 Gen 1 device. The random jitter (RJ) determined with the clock pattern (CP1) is especially noticeable. The corresponding eye diagram for the data pattern (CP0) also exhibits high jitter and noise. The analysis tools provided with the R&S RTP make it possible to investigate the root causes of these problems.
FAST OVERVIEW WITH THE EYE PATTERN Eye pattern analysis is one of the best-known techniques for performing fast signal integrity tests. It involves superimposing the individual data bits of a signal sequence (Fig. 4). Selection of the appropriate timebase for bit analysis is critical here. For all USB standard generations, 2nd order clock data recovery (CDR) is defined with different transfer functions. The eye masks specified in the USB standard have a hexagonal shape (Fig. 5). The minimum height of the eye opening is specified with a value of 100 mV for Gen 1 and 70 mV for Gen 2. The minimum eye width is equal to the bit length (unit interval, UI) minus the maximum total jitter (TJ) that is defined for a bit error rate of 10– 12. For USB 3.2 Gen 1, this value is 68 ps and for Gen 2, it is 28.6 ps. The R&S RTP is equipped to
generate eye diagrams with a configurable CDR that is implemented in the hardware and can be used as a trigger. A continuously running CDR enables a large observation interval for the signal stream that allows detection of sporadic errors. The mask can be configured in the eye centre so that acquisition is stopped when a mask violation occurs. Fig. 6 shows the eye test for the faulty USB 3.2 Gen 1 device that was mentioned above. As was already detected during the conformance test, the eye diagram exhibits a high jitter and noise component. The additional histogram on the right side of the eye clarifies the timing distribution of the bit edges and thus the jitter. The bimodal histogram format reveals some additional information: High deterministic jitter is also contained in the signal.
RESOLVING ERROR SOURCES DUE TO JITTER AND NOISE COMPONENTS A histogram in the eye diagram can provide initial insights into the jitter and noise contained in the test signal. However, in order to gain more detailed information about the interference sources, it is very helpful to break down the total jitter and total noise into the individual components (Fig. 7). For example, high random jitter (RJ) or high random noise (RN) can be a sign of problems in the semiconductor itself (thermal noise, shot noise) or an unstable clock oscillator. Deterministic periodic jitter (PJ) components can arise, for example, due to an unstable PLL or interference from switching power supplies. Data dependent jitter (DDJ) components are divided into duty cycle distortion (DCD), e.g. due to asymmetrical signal edges and intersymbol interference (ISI). The latter can be caused, for example, by transmission losses due to low bandwidth of signal traces or by reflections on vias or connectors. Once the jitter separation is completed, detailed results are available (Fig. 8). The results table (top right) shows that the periodic jitter (PJ) dominates the deterministic jitter. The random jitter (RJ + (O)BUJ) is also noticeably high. The PJ histogram has a distribution that suggests sinusoidal interference. The second table (bottom right) lists the estimated periodic jitter components. Here, high jitter values are noticeable at 100 MHz. This is generally valuable information since the interference frequencies can be tracked back to the corresponding function blocks. Appropriate measures can then be taken to reduce the interference coupling. The power supply is a typical weak point. Interfering signals are easily injected via the supply lines and ground planes. In this example, the R&S RTP generator option was connected to the 5 V supply voltage of the USB device under test. The injected generator signal caused the periodic interference at 100 MHz, while the additional noise resulted in strong random jitter (Fig. 9). Comparison with the situation after switching off the interference source makes this clear (Fig. 10). Once the interfering signal is eliminated, the jitter measurement included in the conformance test passes with no problems.
Instrumentation Monthly September 2022
Fig. 4: The eye pattern is produced by superimposing bit sequences.
Fig. 5: Mask definition from the Universal Serial Bus 3.2 Specification, Revision 1.0.
Fig. 6: Real-time eye pattern for the faulty USB device using hardware based CDR, mask testing and histogram with the R&S RTP164 oscilloscope.
Fig. 7: The total jitter can be divided into random and deterministic components.
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