Monitoring & metering
errors and protect electronic devices from damage. A timing diagram in Figure 2 shows how a reset output is provided when a monitored voltage falls below the UV threshold or exceeds the OV threshold. There are several architecture options of window voltage supervisors for setting the UV and OV threshold and choosing the operating tolerance that can be selected for optimum operation.
Figure 2. A timing diagram showing a reset output in the event of UV and OV.
Any operation of the power supply output can cause problems to the processing and computing device, such as in FPGAs. A regulator with a declared tolerance may not operate exactly at the middle of the output voltage regulation specification, but just within the regulation range. This can be due to the DC error brought by the standard value of resistors used in the feedback loop, which has inherent tolerance, robustness of reference voltage, and optimisation of the feedback loop compensation. Consider an FPGA whose core voltage is supplied by a switching regulator as an example. This switching converter with a declared tolerance of ±2% may operate anywhere within the 4% window. It can be below the nominal value but still within the -2%, therefore putting an FPGA at risk of timing problems. Or it can be near the +2% ceiling, which can still meet the FPGA requirement but is not optimum and wastes a lot of power. Leaving this unmonitored, the device may eventually operate outside of the recommended voltage levels, which can lead to more serious problems and must be avoided.
WINDOW SUPERVISOR TOLERANCE The window supervisor tolerance, or tolerance window, sets the undervoltage (UV) and overvoltage (OV) threshold in terms of percentage with respect to nominal value. For a window voltage supervisor with a nominal voltage value of 1V and a tolerance window
Instrumentation Monthly August 2025
of ±3%, the UV threshold is set at 1V × 0.97 and the OV threshold is set at 1V × 1.03. These thresholds, the UV and OV, however, have their own tolerances known as threshold accuracy.
USING WINDOW VOLTAGE SUPERVISORS
A window voltage supervisor ensures that devices operate within their specified voltage range by setting UV and OV thresholds. It issues a reset output signal if the supply voltage falls outside these set limits, helping to prevent system
However, choosing a window supervisor and using it optimally is not as simple as it seems. The appropriate tolerance window needs to be carefully selected from a range of available variants. Additionally, reset thresholds for UV and OV come with their own accuracy specifications. Threshold accuracy, typically expressed in percentage, is the degree of the conformance of the actual to the computed or target reset threshold, which is determined by a resistor divider and bandgap circuit in the integrated circuit (IC) design. The more robust the reference voltage and the resistors become, the higher the accuracy that can be achieved. Figure 3 shows an illustration of the tolerance window and threshold accuracy in a window voltage supervisor. The actual thresholds of UV and OV, which are the UV_TH and OV_TH, respectively, can vary within the accuracy specification of the minimum and maximum value.
Power supply performance budgeting is often done during system design. For an FPGA core voltage with ±3% tolerance or operating specification, ±1% can be allotted to power supply DC regulation error, ±1% to the output ripple voltage, and another ±1% allowance for transient response. Using a less accurate power supply with ±2% regulation error will leave less allowance for transients. This increases the risk of malfunctions to the device when directly supplied, as transients can go outside the core voltage specification window. Errors can be avoided by using window voltage supervisors to safely put the FPGA in reset mode when this happens.
Figure 3. The undervoltage and overvoltage threshold variation with its accuracy specification. Continued on page 72...
71
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48 |
Page 49 |
Page 50 |
Page 51 |
Page 52 |
Page 53 |
Page 54 |
Page 55 |
Page 56 |
Page 57 |
Page 58 |
Page 59 |
Page 60 |
Page 61 |
Page 62 |
Page 63 |
Page 64 |
Page 65 |
Page 66 |
Page 67 |
Page 68 |
Page 69 |
Page 70 |
Page 71 |
Page 72 |
Page 73 |
Page 74 |
Page 75 |
Page 76 |
Page 77 |
Page 78 |
Page 79 |
Page 80 |
Page 81 |
Page 82 |
Page 83 |
Page 84
