• • • ELECTRICAL EQUIPMENT• • •
HOW TO SHRINK PCB DESIGNS
WITHOUT CREATING THERMAL AND SIGNAL INTEGRITY PROBLEMS
BY CONRAD ELS,
SENIOR HARDWARE ENGINEER, BYTESNAP DESIGN
ost miniaturisation guides present board shrinking as a simple exercise in component selection: swap passives for 0201s, shove them together and let the autorouter handle the rest.
M
Anyone who has actually tried to package power electronics or industrial controls into tight electrical equipment knows that is a fantasy. Shrinking a board is a thermal and EMC decision before it’s a layout one.
Strip away board area, and you also remove copper used for heat spreading and clean return paths, while pushing high-speed traces, power electronics and sensitive analogue circuitry closer together. At the same time, conventional vias consume an increasing share of the available routing space. The challenge is, therefore, not simply fitting everything onto a smaller PCB, but maintaining thermal performance, signal integrity and manufacturability once it gets there.
Managing thermal dissipation
when airflow isn’t an option Standard multilayer layouts lean on open air and natural convection. Sealed industrial control boxes, IP-rated junction units, and compact motor drives trap heat completely. Place a high-efficiency switching regulator or gate driver next to a microcontroller inside a sealed enclosure, and localised heat spikes build instantly. Without room for bulky external heatsinks, the PCB substrate must act as the primary thermal
conductor. That means dropping plated thermal via arrays directly under the exposed ground pads of power ICs and QFNs to draw heat down into internal planes. Specifying 2oz or heavier copper on inner layers turns those planes into effective lateral heat spreaders, dropping peak operational temperatures without adding a single extra component to the bill of materials.
Consider a real-world project by our electronics design consultancy ByteSnap Design involving a compact, sealed device that had to fit an HD camera with night vision and was packed with a 1GHz processor, Wi-Fi, Bluetooth, an eight-LED infrared array, and a 6.5W audio amplifier. The entire system had to fit into an unvented enclosure barely larger than a tennis ball, built around a board measuring just 68mm in diameter. Sensitive analogue measurement circuitry had to sit directly alongside switching supplies and digital processing. Waiting until after the first prototype run in order to discover thermal throttling or power supply ripple on the analogue front-end would have destroyed the development schedule. By treating heat paths and return- current loops as a unified layout problem during initial placement, the equipment passed rigorous compliance testing on the first attempt without extra physical shielding.
When conventional vias
become the problem Once component density forces a shift to fine-pitch BGAs at 0.4mm or 0.5mm, conventional through- hole vias can become part of the problem. Because they pass through every layer, they block valuable routing space even where the connection isn’t needed.
HDI designs overcome this with laser-drilled microvias that typically span a single dielectric layer. But there are limits. IPC-2226 sets a
18 ELECTRICAL ENGINEERING • OCTOBER 2026
maximum depth-to-diameter aspect ratio of 1:1 or below, while many fabricators prefer around 0.75:1 for consistent copper plating. Push beyond this, and voiding can cause intermittent connections that may only emerge during thermal cycling. Engineers often have to choose between staggered and stacked microvias. Staggered vias cost less and generally offer better manufacturing yield. Stacked vias maximise routing space around dense ICs, but require copper filling and planarisation, increasing fabrication cost. Stackup choices affect signal integrity too. Thinner dielectrics bring signal traces closer to their reference planes, helping to contain signal fields and allowing tighter trace spacing without necessarily increasing crosstalk. As density increases, preserving continuous ground planes also becomes critical: breaking the return path beneath a high-speed trace can create common- mode noise and unwanted emissions.
The commercial reality for
equipment manufacturers Adopting HDI design typically increases board fabrication costs by 20 per cent to 60 per cent per panel due to sequential lamination cycles and laser drilling. For equipment manufacturers, however, looking solely at the bare PCB cost is a mistake.
Shrinking the internal electronics often enables smaller aluminium extrusions, reduced enclosure material costs, and lower shipping weights across production runs. Microvias also frequently allow dense control circuits to route in fewer layers, for example, six rather than ten, offsetting a portion of the HDI fabrication premium. Running these financial trade-offs before committing to a final stackup is the only way to ensure miniaturisation actually makes commercial sense.
www.bytesnap.com
electricalengineeringmagazine.co.uk
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