MICROFABRICATION FEATURE Challenges of 3D chip fabrication
Severine Cheramy, IRT Nanoelec, 3D program director explores the challenges involved with fabricating the latest 3D stacking technology and the methodology being used to overcome these complexities
3
D chip technology recently developed by IRT Nanoelec, an information and
communication technologies R&D consortium of CEA-Leti, STMicroelectronics and Mentor Graphics, has demonstrated the feasibility of scalable digital systems using 3D stacking. The 3DNoC chip is based on a 2D die that can be used in a stand-alone applicative mode, and also in a 3D stack with several dice, to multiply the processing performance of the system. Thanks to the multi-skill environment created by the consortium, a global system methodology approach- including architecture, technology, and design flow- was created for both the definition and realisation of this innovative 3D demonstration chip. The partitioning of the processing section of the architecture was built to satisfy scalability requirements and the communication section that manages data and control exchanges between IP blocks used a packet-switching mechanism in which 3D vertical interconnects were completely integrated in the NoC-layered protocol. Several redundancy and fault- tolerance techniques were implemented to evaluate the trade-off between efficiency and complexity, and their ability to improve yield after assembly (similar to the way existing design-for-manufacturing solutions work for 2D technologies). Asynchronous logic used for router implementation strengthened robustness in vertical links, and made timing closure of the whole 3D chip easier to achieve during the design phase.
KEY CHALLENGES IN 3DNOC TECHNOLOGY Using the 3DNOC technology, several identical 65nm CMOS digital die can be bonded with face- to-back technology to build a stack of processing elements. For the purpose of explaining the technology, we will use a two-die stack (Figure 1). To enable electrical connection between the top die and the BGA, TSV interconnections were created on the bottom die wafer after 65nm CMOS layer creation. Aspect ratio 8:1 (80µm depth/10µm diameter) TSVs were realised using a via-middle process. The deep via etching was achieved with a Bosch process, and followed by the deposition of a SiO2 layer for isolation, a Ta layer as diffusion barrier and a Cu seed layer. The via was then filled with Cu ECD. Finally, a regular back-end was processed with seven Cu layers and an Alupad layer. To ensure the connection between the bottom die and the BGA, large copper pillars (55µm diameter, 40µm height) were created on the bottom wafer Alupad. After TiWCu seed- layer deposition, a negative tone dry-film was
patterned to allow the growth of 25µm Cu and a 10µm SnAg. The final shape of the solder bump was obtained after reflow at 250C. Targeted height was 40µm +/-5µm over the wafer. The second step consisted of the TSV backside electrical contact recovery, which was achieved with the use of a temporary bonding process. Two temporary bonding solutions were evaluated: ZoneBOND solution (using a thermoplastic temporary adhesive) and WSS (using a glass carrier and cured polymer). In both cases, 55µm-thick temporary adhesive was spin-coated on the device wafer, over the solder bumps. After bonding on the carrier wafers, potential interfacial defects that could later lead to process failure (voids/particles) were checked with acoustic microscopy. Void-free bondings were obtained with both techniques. Wafer backside thinning was achieved in three steps: 1) mechanical coarse & fine thinning using standard grinding wheels, 2) dry and chemical/mechanical polishing, and 3) exposure of the bottom copper nails using SF6
Figure 1: 3DNoC stack
etching. Uniformity control of each process step (TSV depth, bonding TTV, planarization) is critical at this point. Indeed, height variation over the wafer must remain in the 5µm range to recover 100 percent of via bottom and still meet yield requirements. Copper nail insulation was achieved with PECVD deposition of 2µm dielectric at a low temperature (150°C). The via-bottom electrical contact was then recovered with dielectric CMP. Finally, 40µm pitch (20µm diameter) copper pillars with CuNiAu metallurgy were directly grown on the bottom of the TSVs for top die connection. Next, the 80µm-thin bottom wafer was successfully debonded with the appropriate technology (mechanical or UV release) and cleaned to remove the polymer of the 40µm bumps. In parallel, the complementary 40µm pitch microbump interconnections were created on the active CMOS top die wafer. They are 20µm in diameter, and were achieved on the TiCu seed layer by depositing 10µm copper and 8µm SnAg. Finally, both top and bottom wafers were
integrated through packaging steps. One requirement of this stack is that both dies are strictly the same size, making it impossible for the packaging to use capillary underfill. A non- conductive paste and thermo-compression process was specifically developed to provide excellent filling and electrical connections between silicon dies, as well as the die and BGA.
MOVE TO FINE-PITCH 3D INTERCONNECTS The next generation of demonstration chip, called “IntAct,” is based on a 65nm CMOS 200mm2
active interposer, which is a backbone Figure 2:
Example of 6 BEOL levels on 6 BEOL levels stacking using hybrid bonding
on which it is possible to bond identical die (for scalability), or different die (using 10µm- diameter µpillars and µbumps) for mixed- technology applications. The active interposer integrates many services: I/O, ESD protection, power management, clock generation, test infrastructure, etc. Development of this technology began in September 2015. Reducing µpillars and µbumps dimensions is a first approach to increasing the interconnect density up to ~ 5µm pitch, but to reach submicron pitch, direct or hybrid bonding technology appears to be very promising (see Fig. 2). Whether for mixed-technology applications or digital applications, fine-pitch technology will significantly change the system architecture, allowing more parallelism in processing and data access. Fine-grained partitioning is a new challenge in 3D chips for both heterogeneous stacking (e.g., BSI imagers) and homogenous digital stacking, but certainly shows promise as a new means of maintaining Moore’s Law!
IRT Nanoelec
www.irtnanoelec.fr/en E:
contact@irtnanoelec.fr
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