Frequency Control I Product News
Enhanced performance
Clive Green looks at the E8000, an innovative GPS controlled frequency and timing source which can significantly enhance the performance of timing applications
T
he choice of a GPS receiver is of great importance in the design of a GPS controlled frequency/time
standard. All GPS receivers make a calculation of GPS time every update interval, often 1 second. However methods of using this information, and communicating it to the outside world, vary. Many receivers only output the 1PPS
timing mark. As the GPS receiver uses an internal clock, its control of the 1PPS output time is limited by the frequency of the internal clock. For example , if the internal clock was 10.23MHz, then the quantization interval would be 97.75ns, and the maximum error on the 1PPS output time would be half this, ie 48.8ns. The time calculation may be more accurate than this, however the accuracy can not be reflected in the timing of the 1PPS output. In order to avoid this quantization
limit, some receivers transmit the expected error of the next 1PPS over their digital interface. An external control processor can in principle make use of this in correcting the 1PPS position, however in practice this is quite difficult to do. A receiver that only outputs a 1PPS
time mark is quite difficult to use because the frequency of the controlled oscillator must be compared with the arrival time of each 1PPS pulse. Frequency is rate of change of phase, when the frequency is measured in Hz, and the phase in radians. If we normalise the frequency as a fractional error from a reference frequency, we get the similar relationship that fractional frequency offset is the rate of change of time. The real problem is that the 1PPS output from the GPS
32 April 2010
receiver, and the frequency of the controlled oscillator are at such different frequencies. The controlled oscillator at 10MHz must be compared with a frequency of only 1Hz. Most simple methods of comparing two frequencies only work for identical frequencies, or frequencies with a low harmonic relationship. The GPS receiver that was chosen for
the design has a programmable frequency output. This is a square wave that is generated from an NCO (a simple version of a DDS without the DAC) clocked from the internal 120MHz clock. Every time the time solution is calculated, the phase of the NCO is adjusted so that the frequency output is accurate. This frequency output means that a phase lock loop can be used to lock the controlled oscillator to GPS time. In fact the digital PLL developed for the Quartzlock A6-CPS clean up loop can be used with very few modifications. A further consideration in the choice of
a GPS receiver is the accuracy of the time solution. A conventional navigation receiver will
have a typical variation in its timing calculation of 0.5 to 2us RMS. This is a random variation caused by noise and ionospheric effects. There will also be a systematic longer term variation due to the satellite constellation continuously changing. A navigation receiver needs at least 4
satellites to calculate a 3D position and time. More satellites will add redundancy, and will thus reduce errors in the position and time calculation. If the position is not correct, then the
1PPS time output will have a systematic error. In order to avoid this, a timing
Components in Electronics
receiver will have a self survey mode where the position is calculated and averaged continuously for several minutes . The termination of the self survey may either be a fixed time interval, or the reduction of standard deviation of the position below a threshold. After the self survey is complete, the receiver switches into position hold mode. A timing receiver operating in position
hold mode will have an RMS jitter on the GPS time calculation of between 5 and 50ns RMS. The GPS receiver chosen for the
Quartzlock designs is the Navsync CW25- TIM, with special software to give a hardware indication of status to the microcontroller used to lock the controlled oscillator. This has a measured RMS jitter on the frequency output and the 1PPS output of about 7ns.
Holdover mode
A GPS receiver used for timing applications will often have a built in monitor of the likely timing accuracy. The algorithm used was developed by Motorola, and is called the TRAIM algorithm. This stands for Time-Receiver Autonomous Integrity Monitoring. If the predicted error in the time calculation increases about a threshold, default 300ns, the GPS receiver will go into holdover mode. In this mode the 1PPS output time is held, and the frequency output is locked at its current frequency. The GPS receiver will also set its digital output low to indicate to the microcontroller that the receiver is in holdover. The microcontroller can then freeze the tuning voltage of the controlled oscillator, putting this into holdover mode.
The problem with this simple design is
that the GPS receiver uses a low quality internal TCXO for its internal clock. When the GPS receiver goes into holdover, it freezes the output time of the 1PPS. However as the 1PPS is timed internally from the TCXO, it will drift and will not give very good holdover performance. What is required is a 1PPS time pulse that is timed from the controlled oscillator. In this way the holdover performance of the 1PPS will be identical to that of the controlled oscillator. If the controlled oscillator is a rubidium standard, then the holdover performance will be a few microseconds a day. The solution to this is to use the GPS
receiver in external clock mode. If this is done then when the GPS receiver goes into holdover, the 1PPS timing will come from the controlled oscillator.
Locking Circuit
The hardware and software used to lock the controlled oscillator to GPS time is a classic phase locked loop implemented digitally using a microcontroller. The hardware and software is very similar to that used in the Quarzlock A6-CPS clean up loop. The frequency output from the GPS
receiver is set to 2.5MHz. This is then compared with divided outputs also at 2.5MHz from the controlled oscillator using a quadrature phase detector. The
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