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Eliminating the power integrity analysis bottleneck from PCB design
Designing and building PCB boards comes with many difficulties. John Carney, staff application engineer, Cadence, talks about how to solve these challenges
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nsuring that a PCB design has sufficient power delivery without requiring excess layers or larger board size is essential. The design team needs to be confident that the PCB has enough copper between the power source and all of the loads to support adequate power delivery to each of these loads. IR-drop analysis has, however, become quite challenging with today’s designs. With the continued necessity of low-power design, core voltage levels have continued to drop - 1.5V or less are now common. As voltage is reduced, current requirements typically increase. At the same time, miniaturisation of electronics means fewer layers and higher densities - in other words, less available area for power nets. There needs to be a faster, more reliable way for IR-drop analysis results to get into the hands of PCB designers, so they can properly manage the power flow through the PDN in their designs and meet aggressive time-to-market goals.
designers for every one PI engineer. With multiple ongoing projects, the PI engineer must juggle simultaneous demands for time-consuming IR-drop analysis work. Given this queue of work, PCB designers aren’t able to get instant IR-drop analysis results. So, the PCB designer ends up having to wait for initial analysis results and
Figure 1: Low voltage level with small margin
PDN challenges in PCB design Because IR-drop analysis is a specialised skill, PCB designers typically face some frustrating PDN challenges. The PCB designer receives multiple instructions from the PI engineer, often communicated by email or a phone call and the designer has to apply all of those instructions and rules to multiple power rails and ICs. The designer must also meet a variety of other system requirements - shrink the design by 20 per cent, remove a couple of plane layers and some capacitors - and do it all by yesterday! Indeed, the communication flow between PCB designers and PI engineers creates some of these challenges. If it is like a typical organisation, there are several PCB
then waiting some more while going back and forth with the PI engineer for additional analysis after every adjustment to the design. Then, there are the communications methods like how a PI engineer can best communicate issues and guidance to a PCB designer? How the PCB designer can communicate solutions to the PI engineer? How can the PCB designer determine if a solution is good? In addition, there hasn’t been a formal
process to tell the designer exactly how much metal to add to their board in response to the IR-drop analysis results. Nor has there been a way to indicate whether enough metal has been added for every power rail in the PCB design. That’s why timely analysis and guidance on the adjustments that need to be made are necessary.
Bridging the gap between IR-drop analysis and PCB design What is needed to bridge the gap between the work of PCB designers and
that of PI engineers? Technology that makes the best use of the unique skill sets of each and that drives faster access to power delivery insights is essential. An ideal solution would first enable the PI engineer to manage the complex setup of the analysis technology - these efforts are in their knowledge domain - and allow the designer to reuse the setup parameters. With this approach, the designer could run and rerun the analysis to gather data while resolving first-order problems. Afterwards, the designer could hand the design over to the PI engineer, who would use the same models and report files, reducing the number of iterations and accelerating the time to volume manufacturing.
Figure 2: Typical PDN challenges in the PCB design process
Accurate, signoff-level PI analysis Cadence provides accurate, signoff-level PI analysis tools based on its Allegro and Sigrity technologies that deliver the capabilities discussed. The Allegro Sigrity PI Base is an integrated layout and analysis solution supporting constraint-driven design. Ideal for both layout designers and PI engineers, the tool can be used to drive decap selection and placement, easily identify and resolve IR-drop issues in the physical layout via automated cross- probing configuration after DC analysis, and perform detailed analysis, compliance, and assessment via add-on options. The tool is integrated with Allegro PCB and IC package design, editing, and routing technologies, providing advanced PI analysis during and after layout. It includes Allegro DRC markers that locate areas requiring layout changes to improve IR-drop. While handling analysis setup, the PI engineer can define pass/fail criteria for various measurements in the PCB design,
giving the PCB designer assurance of what is problematic in the power scheme. For PI engineers that need to perform AC and DC analysis, the Cadence Allegro Sigrity Power Integrity Solution provides a trusted toolset. Sigrity PowerDC is a DC signoff solution that provides electrical/thermal co-simulation for high accuracy, the ability to quickly pinpoint IR- drop and current hotspots, and the ability to automatically identify preferred voltage regulator module (VRM) sense line locations. Sigrity OptimisePI provides highly automated board and IC package AC frequency analysis, identifying impedance issues and suggesting placement locations for EMI decaps. The tool helps balance decap cost and performance, with typical decap cost savings of 15-50 per cent. The Sigrity PowerSI is an advanced signal integrity (SI), PI, and design-stage EMI solution with high accuracy, fast throughput, robust frequency domain simulation, and support for S-parameter model extraction and the Sigrity PowerSI 3DEM Option provides 3D full-wave PDN extraction. These capabilities would empower not only the PCB designer, but also the PI engineer, who would be able to drive the Allegro PCB layout tool to experiment with and implement solutions and propose ideas to the designer. Users can choose to stay in the Allegro PCB design environment, with the Sigrity tools running in the background, or work directly in the Sigrity GUI.
Summary With the right IR-drop analysis tool, PCB designers can quickly gain accurate insights into the power delivery scheme in their design. Armed with this data, they can make timely decisions to optimise power delivery, save weeks from the design cycle, and avoid wasting valuable board space.
Figure 3: Integrated solution provides faster access to IR-drop analysis results during the PCB design process 16 July/August 2016 Components in Electronics
www.cadence.com www.cieonline.co.uk
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