TEST & MEASUREMENT FEATURE
Atsushi Kawamoto, Jesper Steensgaard and Heemin Yang of Linear Technology examine how breakthrough data conversion performance enables a new generation of higher accuracy, lower-cost, automatic test equipment (ATE) systems
ATE SYSTEMS: a new level of data conversion T
he proliferation of complex, high performance, system-on-chip
integrated circuits has placed great demands on the automatic test equipment (ATE) systems used to manufacture them. Many ATE systems require measurement of critical parameters with extreme accuracy as they must be significantly more accurate than the devices they are used to test. Modern ATE systems push the boundaries of state-of-the-art signal processing and require parts-per-million (ppm) accuracy. The design of such systems is highly sophisticated, requiring the highest performance integrated circuit components. At the core of many precision ATE systems is an analogue-to-digital converter (ADC). This plays a pivotal role, translating signals from the analogue domain to digital for digital signal processing. The accuracy and performance of the ADC often defines the accuracy and performance of the overall system.
PRECISION ATE SYSTEM REQUIREMENTS Precision ATE systems require high- resolution ADCs to digitise real-world analogue signals. Excellent DC specifications are typically required for the analogue signal chain, including the ADC and supporting signal-conditioning circuitry. In order to achieve ppm-level
resolution and accuracy, many precision ATE systems are digitally calibrated to null out any system-level offset and gain errors. As a result, system accuracy is often limited by errors that cannot be suppressed by infrequent calibration and system designers may be more concerned with potential drift of key parameters than they are with their static values. For example, precision ATE systems may require not only ppm-level accuracy at a fixed temperature, but also sub-ppm/C drift accuracy over a wide operating temperature range. ADC linearity is of critical concern for overall system accuracy. ADC linearity is
determined by complex interactions between the analogue input signal and the ADC’s internal design and architecture. ADC nonlinearity errors are extremely difficult to calibrate at the system level, since such errors vary substantially from one digital code to another and because they may be a strong function of temperature. ADC linearity and stability over temperature are crucial for the overall accuracy of precision ATE systems. To meet these design challenges, a new family of 20-bit SAR ADCs provides a higher level of performance and accuracy, simplifying the design of high-precision ATE systems. Linear Technology’s LTC2378-20 is the flagship product in a family of pin- and software- compatible SAR ADCs featuring up to 20-bit no-missing-codes resolution and up to 104dB SNR at sample rates from 250ksps to 2Msps. The ADC integral nonlinearity (INL) errors of the LTC2378-20 are typically less than 0.5ppm, and are guaranteed to be less than 2ppm, for all codes over the entire operating temperature range from -40°C to +85°C. The offset error is 13ppm (maximum) with 0.007ppm/°C drift, and the gain error is 10ppm with 0.05ppm/°C drift. This performance is achieved while operating at very low power, from 5.3mW at 250Ksps to 21mW at 1Msps. Each device is available in small MSOP-16 and DFN-16 packages.
CHARACTERISTICS OF SAR ADCS SAR ADCs are characterised by their ability to acquire a precise snapshot in time of an analogue input signal and to complete an analogue-to-digital
Complete 20/18/16- bit pin-compatible SAR ADC family
conversion operation within a single clock cycle. SAR ADCs have asynchronous ‘start-and-go’ operations and they are easy to use because the conversion result is available immediately within the same clock cycle. The ability to produce accurate conversion results with no cycle latency, even after long idle periods, makes SAR ADCs suitable for many precision ATE systems. Other types of ADCs, such as delta-sigma and pipelined ADCs, require multiple clock cycles to complete a single conversion.
CIRCUIT ARCHITECTURE The LTC2378-20 has been designed using a proprietary architecture that ensures linearity and minimises its sensitivity to changes in temperature and other operating conditions. As a result, the company says a 2ppm INL specification is guaranteed over the entire operating temperature range. The SAR ADC algorithm is based on a
binary-search principle. The analogue input is sampled onto a capacitor and is compared sequentially to fractions of a reference voltage selected by the SAR algorithm. The SAR ADC comprises three critical components: a capacitor- based digital-to-analogue converter (CDAC), a fast low-noise comparator circuit and a successive-approximation register. The INL performance of a conventional SAR ADC may be limited by finite matching accuracy of individual capacitors in the CDAC, and many precision SAR ADCs employ analogue or digital trimming techniques to improve the matching accuracy. However, as temperature varies and package and board stress is applied, CDAC capacitor
INSTRUMENTATION | DECEMBER/JANUARY 2017
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