Aerospace & Defence
Data processing onboard
As Xilinx explain, new space grade Virtex FPGAs will accelerate the acquisition of image data and enable in- flight processing on scientific space instruments
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emote sensing instruments on spacecrafts deliver vast amounts of high resolution image data. For classical Earth observation missions, scientists typically evaluate the collected data after reception on the ground. While deep space missions also have to cope with high imaging data rates, the telemetry rate, on the other hand, is very limited. One demanding example is the Polarimetric and Helioseismic Imager (PHI) instrument, which has been selected as part of the scientific payload for the European Space Agency’s Solar Orbiter mission, due to launch in 2017. The PHI instrument will provide maps of the continuum intensity, magnetic field vector and line of sight velocity in the solar photosphere. Because of the high amount of
captured data and the limited downlink capability, extracting scientific parameters onboard the spacecraft will reduce the data volume dramatically. As a result, scientists will be able to take a closer look into the solar photosphere. To cope with these
onboard processing demands, the Xilinx SRAM- based FPGAs with high gate counts offer an attractive solution. The team at the Braunschweig University of Technology in Germany has already used the Xilinx devices, and for the Solar Orbiter PHI processing unit, the
university decided to use two space grade Virtex-4 FPGAs, which will be reconfigured during flight.
The Solar Orbiter PHI The PHI instrument acquires sets of images from an active pixel sensor. A filter wheel in the optical path applies different wavelength and polarisation settings to these images. By preprocessing the captured image data and performing a compute intensive inversion of the radiative transform equation (RTE), it’s possible to
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preprocessing core retrieves the previously stored data from the flash memory and performs dark and flat field correction, addition, multiplication and convolution of frames.
For communication to the spacecraft and the system controller, a dedicated GR712 LEON3-FT processor ASIC is used, running at a clock frequency of 50MHz. The CPU has its own 2Gbit SDRAM memory and is also connected to 1Gbit of non-volatile NOR flash memory that stores software and FPGA bitstream configuration files.
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calculate magnetic field vectors from pixel data. Together with standard data compression, this approach will reduce the amount of data from 3.2Gbits to 100Mbits per data set. The processing flow of the PHI can be divided into two modes of operation, and changing between these two modes is perfectly applicable for in-flight reconfiguration of the Virtex FPGAs. During the acquisition phase, the detector provides images with a resolution of 2,048 x 2,048 pixels. The acquisition FPGA will accumulate a set of multiple images at different filter settings and directly store them in a large array of NAND flash memory. To reduce residual spacecraft jitter, a dedicated controller for an image stabilisation system will run simultaneously. After the data acquisition, the two
Virtex-4 FPGAs are reconfigured with a preprocessing core and an RTE core. The
For the image acquisition, image stabilisation, preprocessing and RTE inversion, two Virtex-4QV FPGAs are used. The possibility of in-flight reconfiguration allows the two devices to be utilised in a time shared manner. This scheme reduces mass, volume and the power consumption of the platform. A one time programmable, radiation
hardened FPGA connects the LEON3 system controller and the two Virtex-4 devices. Furthermore, this same FPGA functions as a system supervisor. It provides I/O signals and interfaces to control parts of the hardware and the external power supply, and to communicate with sensors and actuators. Two JTAG interfaces allow this FPGA to write and read back the configuration bitstreams of the two Virtex- 4 devices. To store the large amount of image data, a memory board was designed based on an array of NAND flash devices with a total capacity of four terabytes. To address this set of memories, located on a separate board, a NAND flash controller was developed that is also placed in the system supervisor FPGA. To cope with the relatively slow data rate between the NAND flash array and the processing FPGAs, the data acquisition and preprocessing rely on a fast, external buffer memory. A dedicated network connects the system controller FPGA with the two Virtex-4 FPGAs off-chip and the NAND- flash memory controller with the processing cores on-chip.
Dealing with radiation effects The Xilinx Virtex-4QV is a radiation tolerant FPGA, which means that the device will not suffer physical damage through radiation effects. Nevertheless, bit upsets can occur and the design has to mitigate them. Radiation can affect SRAM-based FPGAs in two layers - the configuration layer and the application layer. Bit upsets in the configuration layer will mainly alter routing logic and combinational functions. One way to repair errors introduced into this layer is to overwrite the configuration SRAM in certain time intervals - a technique known as scrubbing. Here the scrubbing process is optimised by doing a read back on the bitstream. Radiation effects induced into the application layer will result in faults of the control logic, for example stuck state
machines, or simply wrong values in the data path. Here triple modular redundancy (TMR) and error detection and correction (EDAC) techniques are used to mitigate the upsets on this layer.
For a successful mitigation of upsets in the FPGA design, it’s crucial to create mechanisms to protect both the configuration layer and the application layer. Integrating only one mitigation scheme alone (scrubbing or TMR), would not be sufficient. The space grade Virtex-4QV devices are
delivered in a ceramic package. Maintaining a compatible footprint, these devices are equipped with solder columns. Virtex-4QV parts were used in 2012 and no qualified process manufacturer was available in Europe to assemble these CF1140 packages. For this reason the university had to start a mission specific package assembly qualification. For this purpose, three representative qualification boards were assembled with six CF1140 daisychain devices. After dedicated shock and vibration tests, a thermal cycling test with close monitoring of resistances of the daisychain packages was performed. Before and after each test step, optical and X-ray inspection of the devices proved that no critical physical damage had occurred.
Current status and outlook After defining a basic architecture for the design, including error mitigation and the qualification of the Virtex-4 assembly, work began on a prototype of the data processing unit based on commercial parts. This engineering model fits the final 20 x 20cm shape of the electronic housing and is already in operation without major problems. It has a mass of 550g and consumes less than 15W. Currently the focus is on finishing the qualification model of the board, equipped with qualified parts. In summary, the high gate count and the ability for in-flight reconfiguration of the Virtex-4 devices made it possible to develop a compact and high performance data processing platform with reduced size, mass and power consumption. The data flow of the acquisition and processing suits a system with two reconfigurable FPGAs.
www.xilinx.com www.cieonline.co.uk
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