HIGH PERFORMANCE COMPUTING
NVSwitch g
I was going to need the HBM memory for machine learning and things like matrix multiplication but we have really done a good job of reusing data on the FPGA. For instance in machine learning if you have got a model with 20 to 40 layers we will pick part of the image and drill through all the layers as well, which gives us a really high data reuse rate,’ said Strickland. ‘Beyond networking there are
opportunities in data analytics so you can kind of think of it as a caching tier now – a very high bandwidth caching tier – so you can expect to see some applications there as well,’ Strickland added. Intel PSG is also targeting AI research
and recently announced how Bing Intelligent Search is using FPGA technology is powering AI platforms. Reynette, Au vice president marketing
for Intel’s Programmable Solutions Group commented: ‘In today’s data-centric world, users are asking more of their search engines than ever. Advanced Intel technology gives Bing the power of real- time AI to deliver more intelligent search to users every day. This requires incredibly compute-intensive workloads that are accelerated by Microsoft’s AI platform for deep learning, Project Brainwave, running on Intel Arria and Intel Stratix FPGAs.’ ‘Intel FPGAs power the technology that
allows Bing to quickly process millions of articles across the web to get you contextual answers. Using machine learning and reading comprehension, Bing will now rapidly provide intelligent answers that help users find what they’re looking for faster, instead of a list of links for the users to manually check.’ Intel is keen to demonstrate that it is not just GPUs that can deliver AI performance, and the repetitive nature of tasks like inference and training or AI deep learning
6 Scientific Computing World April/May 2018
networks could prove a good candidate for FPGA optimisation. ‘Intel FPGAs are making real-time AI possible by providing completely customisable hardware acceleration to complement Intel Xeon CPUs for computationally heavy parts of the deep neural networks while retaining the flexibility to evolve with rapidly changing AI models and tune to achieve high throughput and maximum performance to deliver real-time AI,’ concluded Au. While some of the biggest players in both HPC accelerators and CPUs are waging war over the AI revolution, AMD has been quietly developing its latest CPU platform EPYC to compete with the latest Xeon CPUs. The company had success in the headlines at the end of last year when the new range of server products were released but, as Greg Gibby, senior product manager of data center products at AMD notes, that he expects the company will begin to see some momentum as several ‘significant wins’ have already been completed. ‘If you look at the HPC customer set
these guys tend to be leading-edge. They are willing to go do ‘unnatural acts’ to go get every ounce of performance out of an
“If you look at the HPC customer set these guys tend to be leading edge. They are willing to go do ‘unnatural acts’ to go get every ounce of performance out of an application”
application. You have seen that through things like GPU or FPGA acceleration where HPC users are willing to go change code and other things to go get every bit of performance they can,’ said Gibby. ‘I believe that as we get customers
testing the EPYC platform on their workloads they see the significant performance advantages that EPYC brings to the market. I think that will provide a natural follow through of us gaining share in that space. Towards the timing and how soon that will all happen I cannot say specifically but I think you will see in 2018 that we will make some pretty significant advances,’ Gibby added. Gibby noted that one thing he thought
would help to drive HPC customers to the AMD platform would be the number of PCIe lanes available to users in a single socket: ‘We have a no-compromise, one- socket system, and what I mean by that is if you look at the way our competitor has designed its platform the PCIe lanes are tied to the CPU, and with Sky Lake you get 48 PCIe lanes on each processor. If you wanted to attach a number of GPUs or if you wanted to have a lot of NVMe drives you have got to buy a two-socket system.’ ‘Now you have got some latency where
you have to go from socket to socket and a lot of times you end up with limitations on the PCIe lanes, which require you to put in a switch. With our solution because you get 128 PCIe lanes off that single socket you no longer have that limitation. You can put 24 NVMe drives or up to six GPUs all on a single socket without having to introduce latency and cost adding PCIe switches.’ ‘That is one thing that is a little bit unique which I think could be potentially disruptive in the market when it comes to the HPC side,’ Gibby concluded.
@scwmagazine |
www.scientific-computing.com
NVIDIA
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40
