Feature: Sensors


Integrating ASICs into next- generation radar systems


By Ross Turnbull, Director of Business Development, Swindon Silicon Systems T


he evolution of radar is oſten described in soſtware terms, with emphasis placed on soſtware-defined modes, adaptive sensing and digital control. But, we are now seeing


a more significant shiſt that is architectural, focusing on how control and signal integrity are maintained as systems scale. Te demand for higher-resolution sensing,


multi-function operation and reduced platform footprint is driving a step change in radar system complexity. As array sizes increase and channel counts scale into the thousands, traditional distributed designs are coming under pressure from power, thermal and interconnect constraints. Modern radar systems, particularly active electronically scanned arrays (AESAs), are moving toward highly parallel implementations in which beamforming, signal conditioning and control functions sit close to the antenna aperture. In a phased array, the beam is steered by controlling relative phase, and oſten amplitude, across the antenna elements. Tis architectural shiſt is driven by


24 June 2026 www.electronicsworld.co.uk


the need for greater bandwidth and responsiveness, but it also means that soſtware performance is increasingly dependent on whether the underlying electronics can sustain coherence and timing accuracy under real conditions. A critical point in this architecture is


the gate-driver stage ahead of the transmit field-effect transistors (FETs). It forms the boundary between digital control and RF power generation, where repeatable behaviour is most difficult to maintain. Small variations here propagate directly into transmit performance.


From RF front-end to control boundary At the element level, AESA radar relies on dedicated, highly optimised circuitry. Each antenna element, or sub-array, is associated with a transmit/receive module containing dedicated RF circuitry. Te transmit path comprises phase and amplitude control followed by a driver stage and a FET-based power amplifier, while the receive path consists of a limiter,


a low-noise amplifier and downstream processing. On the transmit path, high-power RF


devices such as gallium nitride (GaN) are oſten selected for power density and efficiency, while low-noise receive functions may still rely on technologies like gallium arsenide (GaAs) or RF complementary metal-oxide semiconductor (RF-CMOS). Where functions move into RF-CMOS at higher frequencies, designers operate closer to transistor limits with reduced voltage headroom and greater sensitivity to parasitics and substrate coupling. Te gate-driver boundary remains upstream, at the point where digital control is translated into repeatable electrical behaviour, which is the final point where robust control can be applied before RF power is generated.


Signal characterisation at array scale As systems scale, previously negligible effects become dominant. Signal characterisation therefore extends beyond amplitude and frequency response. It


Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44