Feature: Embedded
Figure 1: SystemC/C++ high-level design flow
electronic systems companies. Tese tools are particularly popular as a method to rapidly generate design components with varying microarchitectures, whilst rapidly and effectively optimising algorithm-processing data paths. Teir use on control logic, as well as components with more detailed timing in general, is also becoming more widespread.
Verification requirements for SystemC/C++ designs
By Vlada Kalinic, SystemC Verification Product Manager, OneSpin Solutions
platform models for early soſtware test, configurable intellectual property (IP) blocks, and many more. HLS, which transforms “mostly untimed” abstract SystemC/ C++ design representations to fully-timed register-transfer-level (RTL) design blocks, is in use at many large semiconductor and
A 24 June 2021
www.electronicsworld.co.uk
lthough SystemC/C++ coding styles have been used for many years, specific models have recently emerged to drive common design flows across engineering teams. Tese include abstract algorithmic design code as input for high-level synthesis (HLS) tools, virtual
Verification of System C/C++ Te verification of SystemC/C++ designs is largely performed by compiling the design representation using a standard soſtware compiler, such as GCC, and debugging the code in a similar fashion to soſtware designs. Te Open SystemC International (OSCI) SystemC/C++ class library, now standardised as IEEE 1666-2011, introduced a functionality that provides a more RTL- simulation-like user experience. Still, there are many issues that make the verification of SystemC code a complex, arduous task – including debug runtime performance and test complexity. Te availability of formal techniques at this level has been sparse. A common SystemC/C++ HLS flow makes use of algorithmic
descriptions oſten using only C or C++ code. Tese descriptions are tested to ensure that the algorithm itself operates correctly. Te SystemC class library functions are applied to provide minimal hardware detail, such as basic timing, reset functionality, etc., as required by the HLS tools. Te synthesis tool produces RTL code, which is then applied to a more traditional design-refinement flow and verification process. Te verification of the design is split between the SystemC and
RTL levels. It is clear that engineers would prefer to verify and debug the original SystemC designs, and only check for functional equivalence post-synthesis, similar to traditional RTL development processes. However, the lack of effective SystemC/C++ design verification environments has driven engineers to more traditional HDL verification. As they raise the abstraction level of their design approaches, it becomes more natural to also raise the level of verification. At the pre-HLS algorithmic level, verifying the design directly against its specification with less concern for coding detail
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