Column: JESD204 standard
Synchronising multiple ADCs with JESD204B
By Ian Beavers, Applications Engineer, Analog Devices
M
any communications, instrumentation and signal-acquisition systems must be able to simultaneously
sample analogue input signals across multiple analogue-to-digital converters (ADCs). Te sampled data then needs to be processed and synchronised across the inputs – even though each has its own latency, making it quite the challenge for low-voltage digital signalling (LVDS) and parallel-output ADCs.
JESD204B JESD204B provides a framework for high-speed serial data to be sent over one or more differential signal pairs. Tere is an inherent scheme in the interface to achieve coarse alignment across lanes within the JESD204B specification. Data is partitioned into frames with boundaries continuously sent to the receiver. Te JESD204B Subclass 1 interface has provisions for data alignment, down to the sample level across multiple serial lane links or multiple ADCs, by using a system reference (SYSREF) event signal to synchronise internal framing clocks in both, transmitter and receiver. Tis creates a deterministic latency for devices using the JESD204B link. However, there are still many challenges for a system designer to overcome to achieve full timing closure for sampling synchronisation, such as PCB layout considerations, matched clock and SYSREF generation to meet timing, SYSREF periodicity and digital FIFO delays. Te designer must decide how the device
clock and SYSREF signals will be created and distributed across the system. Ideally, they should be of the same swing level and offset to prevent inherent skew at the component input pin. Te update rate of the SYSREF event must be determined as either a single event at startup or a recurring signal that may occur when syncrhonisation is needed. Regarding the maximum clock and
SYSREF signal skew, careful PCB layout is needed to meet setup and hold timing across boards, connectors, backplanes and various components. Finally, digital
16 June 2021
www.electronicsworld.co.uk
FIFO design and signals traversing across multiple clock domains create inherent digital buffer skew within JESD204B transmitters and receivers that must be accounted for and removed in the back- end data processing stage.
The SYSREF consideration System clock generation can come from several sources such as crystals, VCOs and clock-generation/-distribution chips. While system performance will dictate the clocking needs, one must use multiple synchronous ADCs to produce a SYSREF signal that is source-synchronous with the input clock. Tis makes clock source selection an important consideration in order to latch this system reference event to a known clock edge at a particular time. If the SYSREF signal and clock are not phased-locked this won’t be achieved. An FPGA can be used to provide a
SYSREF event to the system. However, unless it also uses and synchronises to the master sample clock sent to the ADCs, it will be difficult to phase-align the SYSREF signal from the FPGA to the clock. An alternative is to provide the SYSREF
signal from a clock generation or clock distribution chip that can phase align this signal to multiple clocks across the system. Using this method, the SYSREF can be a one- shot event at startup or a recurring signal, depending on the system requirements. As long as deterministic latency remains
constant within the system across ADCs and FPGAs, additional SYSREF pulses may not be needed except to help frame particular system data. Tus, a periodic SYSREF pulse for clock alignment can be ignored or filtered until synchronisation is lost. A marker sample for the occurrence of a SYSREF event could alternatively be maintained without resetting the JESD204B link. In order to initiate a known
deterministic starting point for the ADC channels, the system engineer must be able to close timing for the SYSREF event signal distributed across the system. Tis means that the expected setup and hold time, relative to the clock, must be met without violation. A relatively long SYSREF pulse that spans multiple clock cycles can be
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