Column: JESD204 standard
Figure 1: AD9250, AD9525 and an FPGA linkup
used to meet the hold-time requirement, so long as the setup time to the first required clock is also met. To minimise skew, careful attention
to PCB layout is critical in this effort to maintain matched trace lengths for clocks and SYSREF within the system. Tis may be the most difficult part of achieving synchronous sampling processing across channels. Te effort will only get more challenging as ADC encode clock rates increase and multiboard systems become more complex. SYSREF to clock board skew at
components across boards and connectors must be deterministically known for each device by the system engineer. Any remaining interdevice digital and clock skew delays need to be effectively nulled in the FPGA or ASIC. Back-end processing can change the sample order across ADCs and introduce any needed realignment to prepare the data for further synchronised processing. Correction for interdevice sample
skew can be accomplished by delaying the fastest data samples and transmitter latency to align with the slowest data samples in the back-end FPGA or ASIC.
18 June 2021
www.electronicsworld.co.uk As long as
deterministic latency remains
constant within the system across ADCs and FPGAs, additional SYSREF pulses may not be needed
except to help frame particular system data
For complex systems this may involve multiple FPGAs or ASICs, where each needs to communicate its total interdevice sample latency for final alignment. By introducing appropriate elastic buffer delays in the JESD204B receiver(s) to accommodate each specific transmitter latency delay, the interdevice sample skews can be aligned with known determinism across a system.
Subclass 1 implementation Te AD9250 is a 250MSPS 14-bit dual ADC from Analog Devices that supports the JESD204B interface in a Subclass 1 implementation. Tis subclass allows analogue sample synchronisation across ADCs using the SYSREF event signal. Te AD9525 is a low-jitter clock generator that not only provides seven clock outputs up to 3.1GHz but is also able to synchronise a SYSREF output signal based on user configurations. Tese two products, coupled with a selection of fanout buffer products from Analog Devices, provide the framework to accurately synchronise and align multiple ADC data sent to an FPGA or ASIC for processing.
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