Column: Electric Vehicles
conversion to the desired PoL voltage to the VTM, which is a fixed-ratio (1/K factor) converter. Te PRM uses a zero-voltage switching topology, while the
VTM uses a proprietary resonant high-frequency Sine Amplitude Converter (SAC) topology, with both zero-voltage and zero- current switching, to perform the voltage conversion to the PoL voltage. Te VTM is essentially a DC-DC transformer where the voltage is transformed down (termed the K factor), with a ratio of 1/K, and the current is multiplied by the K factor. Te VTM, also known as a current multiplier, is a very-high-current density PoL converter (new products currently achieve 2A/mm2
placed very close to the processor because of its innovative ChiP packaging and high-density integrated magnetics. Tis level of high current density offers great flexibility.
Depending on processor current, designers can choose between lateral or vertical power delivery. In lateral power delivery (LPD), the current multiplier is located alongside the AI processor, either on the same substrate or directly on the motherboard within a few mm, enabling a reduction in PDN resistance to about 50µΩ; see Figure 4. For even higher performance, vertical power delivery
(VPD) moves the current multiplier directly beneath the processor, where its output power pin map matches that of the processor power pins located above; see Figure 5. Te current multiplier package also integrates the high-frequency
bulk capacitors that typically sit beneath the processor on the motherboard or substrate. Tis type of current multiplier is called a Geared Current Multiplier (GCM). VPD reduces the PDN resistance to an incredible 5-7µΩ, enabling AI processors to achieve their true performance capabilities.
), which can be
Complex power problems Complex power problems of this magnitude require a holistic design approach to deliver successful high-performance results. Innovations in architecture, topologies and packaging are required to solve the toughest power challenges, which are increasing in scale. Higher- voltage PDNs can solve many system performance challenges. However, without high density and efficiency, system engineers will not have fully optimised solutions. Reducing PDN resistances is the key to unlocking the next generation power for HPC and enabling the promise of AI.
Figure 4: High-current delivery is provided via the MCM modules that can be placed adjacent to the processor, on either the motherboard or the processor substrate. Placement on the substrate minimises PDN losses and reduces the number of processor substrate BGA pins required for power
Figure 5: Vertical Power Delivery (VPD) further eliminates power distribution losses and VR PCB board area consumption. VPD is similar in design to the Vicor LPD solution, with the added integration of bypass capacitance into the current multiplier or GCM module
16 April 2023
www.electronicsworld.com
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44