Column: JESD204 standard
At the SERDES level, a notable difference
between LVDS and JESD204 is the lane data rate, with JESD204 supporting more than three times the serial link speed per lane than LVDS. When comparing high-level features like multidevice synchronisation, deterministic latency and harmonic clocking, JESD204B is the only interface that provides these functionalities. Systems requiring wide- bandwidth multichannel converters that are sensitive to deterministic latency across all lanes and channels won’t be able to effectively use LVDS or parallel CMOS.
LVDS overview LVDS is the traditional method of interfacing data converters with FPGAs or DSPs. It was introduced in 1994 to provide higher bandwidth and lower power needs than the existing RS-422 and RS-485 differential transmission standards. LVDS was standardised with the
publication of TIA/EIA-644 in 1995. Its use increased in the late 1990s, and the standard revised with the publication of TIA/EIA- 644-A in 2001. LVDS uses differential signals with
low-voltage swings for high-speed data transmission. Te transmitter typically drives ±3.5mA with polarity matching the logic level sent through a 100Ω resistor, generating a ±350mV voltage swing at the receiver. Te
always-on current is routed in different directions to generate logic ones and zeros. Te always-on nature of LVDS helps eliminate the switching noise spikes and electromagnetic interference that sometimes occur when transistors are turned on and off in single-ended technologies. Te differential nature of LVDS also provides considerable immunity to common- mode noise sources. Te TIA/EIA-644-A standard recommends a maximum data rate of 655Mbps, although it predicts a possible speed over 1.9Gbps for an ideal transmission medium. Te huge increase in the number and
speed of data channels between FPGAs or DSPs and data converters, particularly in the applications described earlier, has created several issues with the LVDS interface; see Figure 2. Te bandwidth of a differential LVDS wire is limited to about 1.0Gbps in the real world. In many current applications this creates the need for a large number of high-bandwidth PCB interconnects, each a potential failure point. Te large number of traces also increases PCB complexity and overall size, raising design and manufacturing costs. In some applications, the data converter interface becomes the limiting factor in achieving the required system performance in bandwidth-hungry applications.
JESD204B overview Te JESD204 data converter serial interface standard was created by the JEDEC Solid State Technology Association JC-16 Committee on Interface Technology to provide a higher speed serial interface for data converters to increase bandwidth and
reduce the number of digital inputs and outputs between high-speed data converters and other devices. Te standard builds on 8b/10b encoding technology developed by IBM that eliminates the need for a frame clock and a data clock, enabling much faster single line pair communication. In 2006, JEDEC published the JESD204
specification for a single 3.125Gbps data lane. Tis interface is self-synchronous, so there is no need to consider the length of the PCB wire traces to avoid clock skew. JESD204 also leverages the SERDES ports offered on many FPGAs to free up general- purpose I/O. JESD204A, published in 2008, adds
support for multiple time-aligned data lanes and lane synchronisation. Tis enhancement makes possible higher bandwidth data converters and multiple synchronised data converter channels and is particularly important for wireless infrastructure transceivers used in cellular base stations. JESD204A also provides multidevice synchronisation support, useful for devices that use large numbers of ADCs, such as medical imaging systems. JESD204B, the third revision of the
spec, increases the maximum lane rate to 12.5Gbps and adds deterministic latency, which communicates synchronisation status between receiver and transmitter. Harmonic clocking, also introduced in JESD204B, makes it possible to derive a high-speed data converter clock from a lower-speed input clock with deterministic phasing. Fewer interconnects simplify layout and
make it possible to achieve the goal of a smaller form factor; see Figure 3.
Figure 1: Typical high-speed converter to FGPA interconnect configurations using JESD204A/ JESD204B interfacing
Figure 2: Challenges in system design and interconnect using parallel CMOS or LVDS
Figure 3: JESD204 with its high-speed serial I/O capability solves the PCB complexity challenge
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