FEATURE u Test & Measurement
Non-destructive testing of 3D packages in semiconductor manufacturing
Non-destructive testing of 3D packages with scanning acoustic microscopes identifies defects down to the sub-micron level for 100% inspection, writes Jeff Elliott, US-based technical author
T
he concept behind advanced 3D packaging in the semiconductor industry is to stack multiple dies or
wafers in a vertical direction – or Z-dimension – to achieve better performance with lower power requirements, smaller size and lower cost. However, as 3D packages become
increasingly complex, so do the challenges in identifying defects in multiple layers of stacked dies, silicon interposers and interconnections such as through-silicon vias (TSVs) and fine- pitch micro-bumps.
With less accessibility to internal components and a need to scan multiple, stacked layers, the focus is now shifting to methods of non-destructive testing both in manufacturing and for failure analysis.
3D ADVANCED PACKAGING In general, the term 3D packaging applies to products manufactured by stacking silicon
34 July/August 2021 Irish Manufacturing
wafers or dies and interconnecting them vertically. This covers many integration schemes, including 3D wafer-level packaging, system in package (SiP), package on package (PoP), 2.5D and 3D, stacked ICs and other forms of heterogeneous integration. To achieve vertical stacking, early 3D packages relied on interconnects such as wire bonding and flip chips. Today, communication between chips often involves a silicon or organic interposer or bridge, with TSVs. The interposer acts as the bridge between the chips and the board, while increasing the I/Os and bandwidth. Now, the concept of chiplets is gaining momentum for advanced packaging. In this approach, modular chips – or chiplets – from third-party vendors are used to build a package or system by stacking the components vertically. By selecting the optimum CPU, IO, FPGA, RF or GPU, for example, the chiplets could be mix-and-matched using a die-to-
die interconnect scheme involving a silicon interposer, a silicon bridge or high-density fan- out. This approach has been embraced by Intel, which recently announced its new Foveros 3D packaging technology that allows complex, heterogenous logic chips to be stacked directly on top of each other. Intel uses an active interposer instead of a typical passive silicon interposer. As an alternative, Intel is also offering its silicon bridge technology called Embedded Multi-die Interconnect Bridge (EMIB). The Defense Advanced Research Projects Agency (DARPA), an agency of the US Department of Defense, already plans to develop a large catalogue of third-party chiplets for commercial, military and aerospace applications. The goal of DARPA’s CHIPS program (Common Heterogeneous Integration and Intellectual Property Reuse Strategies) is to increase overall system flexibility and reduce
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