Supplement: Power
Figure 3. The reset timeout period (tRP) helps keep the system in reset mode while the supply voltage stabilises.
parameters that help mask these transients that are associated with the power supply or monitored voltage. These are the reset timeout period, reset threshold hysteresis, and the reset threshold overdrive vs. duration. Meanwhile, for the transients that are associated with the mechanical contact in the circuit such as a push button switch in the manual reset pin, the manual reset setup period, and the debounce time mask the transients. These parameters make the voltage supervisors robust and unaffected by transients and glitches, thus keeping the system from undesirable responses.
Reset timeout period (tRP )
During startup or when the supply voltage is rising up from an undervoltage event and exceeds the threshold, there is an additional time on the reset signal before it de-asserts, which is called the reset timeout period (tRP
).2
the dependability of voltage supervisors when monitoring power supplies to increase the reliability of the system in the application.
Power supply noise, voltage transients, and glitches in a system Power supplies have inherent imperfections. There are always noise artifacts coupled on the DC that can come from the power supply circuit component itself, noise from other power supplies, and other noise generated from the system. These problems can be worse if the DC power supply is a switch-mode power supply (SMPS). SMPS produces switching ripple that is coherently related to the switching frequency. They also produce high frequency switching transients that occur during switching transitions. These transitions are caused by the fast on and off switching of the power MOSFETs. Figure 1 shows an application circuit in which the MAX705 supervisor is used to monitor any failure in the output of the switching regulator, which is the voltage supply of the microcontroller.
Aside from the steady-state operation noise artifacts, there are also scenarios in the power supply where voltage transients are more pronounced. During startup, a voltage output overshoot is usually observed related to the feedback- loop response of the power supply and is followed by voltage ringing for some time until it reaches stability. This ringing can be worse if the feedback loop
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compensation values are not optimised. Voltage overshoot and undershoot can also be observed during transient or dynamic loading. In the applications, there are times when the load needs more current to execute complex processes, which leads to a voltage undershoot. On the other hand, reducing the load instantly or at a fast ramp rate will give a voltage overshoot. There are also short-duration voltage glitches that can occur to the power supply due to external factors. Figure 2 shows an illustration of the different voltage transients and glitches that can be present on a power supply voltage in different scenarios.
There are voltage transients that can occur in a system that are not associated
with the power supply voltage but rather on a user interface such as a mechanical switch or a conductive card for some applications. Turning a switch on and off produces voltage transients and noise on the input pin, typically a manual reset pin. All of these factors - power supply noise, voltage transients, and glitches, if excessive - can unintentionally hit the undervoltage or overvoltage threshold of a supervisor and trigger false resets if not accounted for in the design. This can lead to oscillatory behaviour and instability, which is undesirable with regards to system reliability.
How do voltage supervisors address noise and transients prevent the system from nuisance resets? There are
Figure 4. RESET output response without and with threshold hysteresis (reset timeout period not shown to focus on the effect of hysteresis).
As an example, Figure
3 shows that after the monitored voltage, which in this case is the supply voltage labelled as VCC, reaches the threshold from an undervoltage or startup, an added delay is present for an active LOW reset before it de-asserts HIGH. This additional time gives room for the monitored voltage to stabilise first, masking the overshoot and ringing before enabling the system or taking it out of reset mode. The reset timeout period suppresses false system resets to prevent oscillation and potential malfunction, thus helping improve the reliability of the system.
Threshold hysteresis (VTH+) There are two main benefits of having threshold hysteresis. First, it provides certainty that your monitored voltage has overcome the threshold level with enough margin before de-asserting a reset. Second, it gives room for the power supply to stabilise first before de-asserting a reset. There is a tendency for the reset output to produce multiple transitions when processing signals with superimposed noise, as the power supply bounces and recrosses the threshold region. This is shown in Figure 4.3
In applications such as
industrial environments, noisy signals and voltage fluctuations can occur anytime. Without hysteresis, the reset output will continuously toggle assert and de-assert until the power supply stabilises. It will also put the system into oscillation. Threshold hysteresis cures the oscillation by putting the system hold on reset to prevent the system from unwanted Continued on page 32
Components in Electronics December/January 2025 31
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