WEARABLE TECHNOLOGY & BIOMETRICS
sureCore Limited A
s wearables such as earbuds and smartwatches become increasingly popular, developers are adding additional features to differentiate their products and move them up the value chain. Personal healthcare is a rapidly growing area and these products are ideally placed to monitor key biometric data to help individuals track their health goals. Doing so necessitates new sensor technology as well as substantial software increases. This growing software footprint is driving the inclusion of ever more embedded SRAM and, consequently, higher power needs. For form factor constrained wearables, larger batteries are not an option. The solution is to use ultra-low power memory technology rather than standard off-the-shelf options that have been optimised for either area or speed but not power.
Operation at low and near threshold voltages needs special attention – not least the recharacterization of the logic cell library to adequately model the increased levels of variation caused by the exacerbation of process variability at low voltage levels. Liberty Variation Format with Moments (LVFM) that was originally developed to support leading edge process nodes is now being adopted as an expedient way of modelling behaviour as operating voltages are reduced.
One area that has remained a challenge is that of embedded SRAM. Whilst the logic may be synthesised to operate at near threshold voltages thereby delivering the requisite power savings, the inclusion of SRAM in such circuitry remains a fudge. Underlying this issue is the high-density foundry bit cell. This structure is optimised for packing density and is particularly susceptible to process variation. Statistical minority of a bit cell population (of which there could easily be millions per chip) could be unduly “weak”. This “weakness” typically manifests itself in three major ways; low read current, write-ability and stability. Each of these issues will contribute to data loss and
38 APRIL 2023 | ELECTRONICS TODAY
Low voltage SRAM wearables viable
they are all greatly exacerbated by reducing the bit cell operating voltage rapidly introducing both read and write errors, Dual rail SRAM goes some way to ameliorate this problem by ensuring that the bit cell array is always correctly powered. However, the central problem of multiple supply rails and a ring of level shifters to interface to the memory remain. This approach can, of course, be made to work, but the impact on timing closure means that a high degree of manual intervention is needed which brings a whole series of new challenges.
Just one rail and therefore just one voltage domain
The sureCore EverOn™ SRAM has been
Choice of sleep modes to cut power consumption
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