COMPONENT DESIGN


verifi cation process is imperative to guarantee that the integrated IP blocks function cohesively and comply with all design standards and requirements. Given these chiplets are expected to remain operational for over 10 or 20 years, it presents unique challenges verifying and maintaining these IPs throughout their lifecycle, especially as personnel changes occur over time.


Q: How do design teams improve IP security and ensure compliance in a multi-vendor chiplet design environment?


The wider adoption of chiplet technology has signifi cantly raised the stakes for IP security and compliance. Here are my three recommendations:


First, rigorous access controls play a pivotal role in securing semiconductor IPs. The IP management systems should limit access based on defi ned criteria, this can include job functions, geographic locations and security levels. Given the increasingly stricter export control, design companies must incorporate geofencing capabilities that restrict access to certain IPs based on the physical location of an individual, whether they are contractors, designers or architects. For large-scale, multi-vendor chiplet projects, companies should also consider adding custom checkpoints, such as limiting a specifi c IP to a single design, thereby preventing unauthorised reuse in subsequent projects.


Second, an integral component of managing IP lifecycles is its capability to verify the licensing status of IPs, ensuring that design teams have permission to use them. For chiplet-based designs, this verifi cation process requires visibility on whether an IP has already been used in another project within the company and whether it is available for use in new designs. Such measures are essential for preventing licensing violations and the potential legal and fi nancial repercussions.


Third, precise tracing of IP usage is critical for maintaining security and compliance. This helps streamline engineering change orders (ECOs) and adherence to industry standards like functional safety, such as ISO 26262 for automotive. For instance, an effective IP management approach should be capable of providing detailed reports on the exact usage of an IP, its dependencies and the hierarchy within its designs. This enables IP managers to accurately trace critical information throughout the IP lifecycle, enhancing design traceability with one single source of truth.


OCTOBER 2024 | ELECTRONICS FOR ENGINEERS 13


Q: Can you share some best practices for facilitating collaboration between design teams, especially when they’re working on chiplet-based projects?


First, the shift towards chiplet-based designs has underscored the need for a centralised IP management strategy for robust collaboration. This ensures that every team member works from the latest libraries and traceable lineage for each piece of IP. In a multi-vendor environment, the security of sensitive IP becomes paramount. For instance, when it comes to testing die-to-die interconnects, all team members should gain a clear view of which data can be shared with other vendors and which cannot.


Furthermore, securing data during handoffs, whether through workfl ow tools or between teams, is a critical concern. At Keysight, we have implemented encrypted data transfers and secure fi le-sharing protocols to safeguard IP information. For companies in the aerospace and defence industries, the need for secure workfl ows pushes demand for integrating blockchain technology into IP management.


Q: How do you integrate workfl ows for chiplet designs with various EDA tools?


Integrating workfl ows for chiplet designs with various Electronic Design Automation (EDA) tools is a complex process.


Traditional, home-grown solutions for data import/export become more cumbersome and error-prone. For instance, when integrating different chiplets, how are we verifying the interconnect between chiplet one and chiplet two across the enterprise? How to track the history of an IP to see if it has been successfully used in any previous SoC projects?


All of these types of data exchange and communication should happen within one platform so that everybody knows where to fi nd the data, trace the IP usage and project notes and do an audit report of the IP. With this in mind, companies need a unifi ed environment that integrates with all EDA tools. This way, teams can gain a comprehensive view of all design data and IPs at the enterprise level. By keeping all data and IPs within a unifi ed platform, businesses can also mitigate the risk of siloed information and ensure that all team members can access the latest, accurate versions.


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