TEST & COMPLIAN CE BEGIN WITH


THE TRANSMISSION Understanding the ramifications of DDR5 transmitter tests


Ailee Grumbine, strategic product planner at Keysight Technologies


T he DDR5 specification is designed to for data cent


satisfy large performance demands ers. has been driven by


It


smart mobile technology and exascale computing, along wit h , 100/400GBE IoT he


and 5G, which are now connecting t echnology


world in real time. As new t spaces like artificial intelligence and machine learning develop, DDR5 will become essential.


DDR5 will operat e at double the speed of its predecessor. While this brings exciting possibilities, the increased speed means t here are several characteristics of the signal that must b ested and verified differently than DDR4.


e t


Validating the data window wit h ey diagrams and receiver masks is a key es at


e


task for the designer. DDR5 operat a hy per speed of 6400MT/s. If an open


eye can be achieved, the tests used for age of DDR4 will also apply


the design st


to DDR 5. If not, one may need to use t echniques like equalisation to open the DDR5 eyes, often done with serial buses.


Signal integrity


NOISE AND JITTER INTERFERENCE is a big issue in


and data signals or identify


characterising DDR L egacy methods, such as using strobe ing the read


and write pre-amble pat tern, may no longer apply. Jitt er may also become an important component for design characterisation. Fast er data rates, especially at speeds over 3600MT/s, e to close.


placed on noise and jit 5 DRAM transmitters. e t


, examines the complexities of characterising DDR5 DRAM transmitters


will also be required if there is no eye. It may b hat an equalisation method requires an eye diagram measurement.


GAINING ACCESS Before we can perform any characterisation, one needs access to the signals of interest : clock, st robe, data, and command. If available, circuit vias are the best place to access these signals because one can examine and h he DR AM. Via


interact directly wit t


access is limited, especially when boards are loaded wit h multiple devices, with as


lit tle keep out volume as possible. ion is to use a BGA


T he next opt


interposer, which routes out all signals of interest for testing. Soldered to the board he AM is


using a BGA rework station, t DR then soldered onto t he erposer. One int


must not break the bus when loading t interposer, so designers should ensure he


that the int erposer can handle t signal speed.


S paramet


T his can be achieved by using the er files in de-embedding


software, t o build a transfer function file t hat corrects the signal’s frequency response. At dat a rates above 3000MT/s, DDR5 may require equalisation to


improve the data ey by the receiver. In DDR5, one must characterise timing and signal integrity to guarantee that these meet clock, st robe, data and voltage requirements.


may cause the ey Therefore, when choosing test equipment, consideration should be ter performance.


New methods t o characterise the data T t e after being latched he Ailee Grum


product planner at Keysight T


mbine, strategic planner at Technologies


For jitter jitter com on an osc


characterisation, one must be able to separate random and deterministic mponents. Here’s an example: an N-unit interval jitter measurement setup, cilloscope, to measure random and deterministic jitter


b bl be able to separate deterministic jitter


For jitter characterisation, one must i ji


d noise, or crosst i i


components to identify the source of any alk. DDR5’s complexity


warrants design cycles, including simulat ion and compliance test s.


T he design workflow should allow data analytics to perform a measurement correlation between simulation, the design of experiments and compliance. Modern simulation tools allow output of waveform files to be used in the compliance test soft ware for early


or opt


testing, before a real device under t est is available. If any tests fail, early redesign imisation can be performed with


the help of a dat a analytics tool. When an actual device under t est is available, measurement correlation can further refine the performance and margin of t he design.


The key to successful DDR 5 transmit testing depends on what t ools you use. A complete DDR5 transmitt er solution f b


ill ter


consists of a probe, an oscilloscope and a compliance or validation software which covers all the t est speed and t est parameters. When choosing an


d


oscilloscope, make sure it has the lowest jitter and noise int erference. While you he measurements manually


can perform t


wit h an oscilloscope, translating the test paramet ers into measurement steps can be t ime consuming. An automated


TESTING THE LIMITS he DQS2DQ test measures write cycle he DRAM, telling the DRAM


timings to t designer how much skew is allowed by the controller for DDR5.


/ ELECTR ONICS


software package can be used for compliance or validation to ensure interoperability and repeatability.


Keysight Technologies www.keysight.com


ELECTRONICS | M AY 2019 27


FEATUREAT


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