POWER
When trying to cut a chip’s power needs, don’t forget the memory…
Paul Wells, CEO, sureCore F
or SoC product developers, worrying about the impact of memory power consumption is often way down the list of care-abouts. Indeed, it is enough of a challenge just juggling the demands of meeting feature, performance, area and system power goals. Typically, as memory IP is often sourced from the foundry or one of the big IP vendors then the power that they quote is the power you get; end of discussion. However, given that on-chip memory can now account for more than 50
of the overall power budget too, then maybe it is time this critical element got bumped up that list.
The trend to use ever more advanced nodes continues unabated across the semiconductor industry in order to deliver more features at lower cost and power. However, for most off-the-shelf memory IP, the design optimisation criteria were often driven by the needs of the High Performance Compute or Mobile sectors delivering
42 DECEMBER/JANUARY 2025 | ELECTRONICS FOR ENGINEERS
performance at the cost of power. Even for AI chip designers where performance is critical, standard memory solutions can mean eye watering power demands as more and more data needs to be transferred to and from the processor. This is a growing problem in a wide range of applications with the most obvious being wearables, where there is a limited amount of battery power, and yet to remain competitive, developers need to add ever more functionality. This inevitably
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