high-performance computing
Future technologies
Robert Roe investigates the use of technologies
in HPC that could help shape the design of future supercomputers
I
n addition to the normal annual progression of HPC technology, 2017 will see the introduction of many technologies that will help shape the future of HPC systems.
Production-scale ARM supercomputers, advancements in memory and storage technology such as DDN’s Infinite Memory Engine (IME), and much wider adoption of accelerator technologies and from Nvidia, Intel and FPGA manufacturers such as Xilinx
www.scientific-computing.com l
and Altera, are all helping to define the supercomputers of tomorrow. While the future of HPC will involve myriad
different technologies, one thing is clear – the future of HPC involves a considerably greater degree of parallelism than we are seeing today. A large driver for this increased parallelism is the use of increasingly parallel processors and accelerator technologies such as Intel’s Knights Landing and Nvidia’s GPUs. However, in the opinion of OCF’s HPC and
storage business development manager David Yip, the lines between accelerator and CPU are blurring. Tis requires HPC developers changing their mindset in order to evaluate the kind of technology they want in their HPC systems. Yip highlighted that, in the past, there have
been other accelerator technologies. However, they were not realised at the correct time, or
@scwmagazine
the critical mass needed to reach widespread adoption was not reached – so the technology was slowly surpassed by rivals. ‘What hampered their take up 5 to 10 years ago was the soſtware, and how hard it was to program these very complicated systems. Our brains do not naturally think about the kind of extreme parallelism we are now seeing in HPC,’ stated Yip. Tis increasing number of computing cores,
either through CPU or GPU, also impacts the way that HPC programmers must manage and develop their applications. As larger and larger numbers of small processing elements become commonplace, HPC developers need to address this in the way that they program algorithms and map them onto the hardware available. ‘Over the last 10 years we have had to get
used to MPI programming on compute cores, ➤ FEBRUARY/MARCH 2017 13
Deniseus/
Shutterstock.com
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32
