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high-performance computing


term – wafer level stacking. Tese wafers are then thinned by grinding down the unnecessary material; the circuits are on the face of the wafer, so the wafer is put on the turntable face-down, and the blank backside is ground away. Tis process must be handled carefully


because if a wafer gets too thin, it becomes weakened. To overcome this, Tezzaron bonds two wafers together, face-to-face. Tis enables the company to produce stacks of wafers much thinner than is normally possible. Tezzaron claims that they can create memory wafers that are approximately 1/10 the thickness of wafers produced by their competitors. Another technique that Tezzaron employs


during the manufacture of its memory is the use of extremely small tungsten contacts connecting these wafers. Te small wafers enable the use of smaller contacts, and this allows up to 100 times as many vertical wires throughout the memory stack. Although this manufacture method is


slightly more expensive, Chapman believes this will be minimised at sufficient scale. ‘We believe that, once in volume, it will be significantly cheaper. Te technology will become relatively less and less expensive over time, as other approaches to increasing transistor density per unit area of silicon continue to rise in cost at an exponential rate.’ Because Tezzaron has so many vertical


latency to the overall architecture, as opposed to going through SATA controllers and onto rotational disk.’ ‘It’s kind of like SSDs on steroids for


making sure that you have a well-balanced architecture’ concluded Power. Another company that is trying to make


significant changes to memory technology is the memory manufacturer Tezzaron. Tezzaron specialises in designing and manufacturing memory using transistor- level 3D technology. Tis strategy focuses on stacking transistors instead of just making them smaller. Tese stacked circuits are called ‘3D-ICs’. David Chapman, VP of marketing for


Tezzaron, said: ‘Te Tezzaron method requires changes on several different fronts simultaneously; basic chip architecture, circuit design, debug, test and packaging. Naturally, that includes new silicon processing techniques as well.’ Tezzaron stacks complete wafers before they are cut into individual dies, hence the


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wires in the chip, there are more connections available for fine-grained repair. Tat means that more defects can be repaired in each chip. Tese intricacies enable the company to design built-in self-test and repair technology BiSTAR. While increasing memory bandwidth is the


most obvious option to increasing application performance. Micron, a provider of memory and storage products, has been working on a new emerging technology called Automata Processing. Tis project focuses on reducing the amount of data that needs to be moved across the network into the CPU, rather than increasing memory bandwidth. ‘You can think of this as being a massive


regular expression pattern matching engine. Before you need to move the data onto the CPU to do the computation or check against it you can cleanse a massive amount of information in regular expressions before it even gets to the CPU’ said Power. Power explained that Boston has been


working with some early prototypes of this technology: ‘Tis is another product that we have in the lab that could potentially revolutionise the way that memory is used.’ He explained that, in its first incarnation,


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this technology would be a PCI add-on, but future generations would likely be based on a memory DIMM form factor. ‘Tis is a hugely exciting area of research


that we are engaged in with Micron. It could have major implications for any application that is big data or analytically orientated’ said Power.


THERE IS A


SCENARIO WHERE YOU WOULD SEE A HYBRID BACK-END COMPRISED OF MEMORY AND STORAGE THAT WILL USE MEMORY AS YOUR MAIN STORAGE RATHER THAN HAVING A THIRD TIER OF DISK


Micron’s Automata Processor (AP) is a


programmable silicon device, capable of performing high-speed, comprehensive search and analysis of complex, unstructured data streams. Unlike a conventional CPU, the AP is a scalable, two-dimensional fabric comprised of thousands of interconnected processing elements, each programmed to perform a targeted task or operation. Te Automata Processor PCIe board is


the first platform to host Micron’s Automata Processor technology. Te design uses an Altera FPGA to bridge a communication interface between a host server and several ranks of Automata Processors on two different channels. Although the technology is still in


development, Micron released an SDK earlier this year. Te SDK includes a visual development environment, compiler, design rules checker, and simulation tools, to enable developers to build, compile, simulate, and debug their designs. Another project set to make a large


impact on the HPC industry is based on collaboration between Intel and Micron. Te technology, known as 3D XPoint, is a new class of non-volatile memory. Intel has claimed that throughput could be up to 1,000 times higher than flash memory. Tis technology, similar in concept to


Diablo’s memory storage technology, will enable high-speed, high-capacity data storage close to the processor, significantly decreasing latency compared to today’s technology. ‘Tis could potentially eradicate the need


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