MCUS & MPUS FEATURE Creating a faster paced life
make embedded connectivity more secure. A full-featured hardware crypto engine, with a random number generator, provides high-throughput data encryption/decryption and authentication, such as AES, 3DES, SHA, MD5 and HMAC. Beyond the high performance core and
communications-oriented peripheral set, the device also features two further innovations, both of which are intended to address emerging real-world needs of the target applications; both innovations deal with the need for more sophisticated memory systems. An increasing number of OEMs are
Bill Hutchings, Senior Product Marketing Manager, MCU32 at Microchip explores the latest addition to the company’s PIC32 family and how these devices are offering increased performance, integration and faster processing for connected devices
I
f there is one characteristic that all modern devices strive to demonstrate
— irrespective of the end application — it is responsiveness. The ability to react ‘immediately’ is, of course, an illusion, sustained by the speed with which the microprocessor can respond to an event. Improving the response time of a
microprocessor is often closely influenced by the software it executes, however the underlying metric is the theoretical maximum number of instructions that can be executed per second, or MIPS, subsequently improving this figure has long been the driver for microprocessor evolution. There are a number of recognised techniques for pushing performance up, as measured using the industry-standard unit of Dhrystone MIPS, or DMIPS. The latest member of Microchip’s PIC32 family of high performance microcontrollers, the PIC32MZ, harnesses the latest MIPS32 core from Imagination Technologies, which combines many of these techniques to deliver a device that increases performance threefold over its predecessor. The core at the heart of this latest
microcontroller is the recently announced MIPS microAptiv core, which features DSP
/ ELECTRONICS Figure 1:
Microchip’s PIC32 family of high performance microcontrollers, the PIC32MZ, harnesses the latest MIPS32 core from Imagination Technologies
extensions and the microMIPS instruction set architecture, which allows a combination of 32- and 16-bit instructions to run from memory at near- full rate. In addition, the entire device is capable of running at up to 200MHz, which together results in a device that delivers 330 DMIPS; three times the performance of the PIC32MX family.
ACCELERATED DSP PROCESSING The microAptiv DSP extensions provide 159 additional instructions providing single-cycle access to the microarchitecture features that accelerate digital signal processing, such as multiply/accumulate. This means DSP algorithms can execute in as much as 75 percent fewer instruction cycles than the same algorithm executing on the PIC32MX. This is the first family to use the microAptiv core, which as mentioned also introduces the microMIPS feature of 16-bit instructions, resulting in significantly higher code density; as much as 30 percent greater density than the previous generation. An important aspect of any connected
device today is security and, here, a number of features are integrated to
finding that the growing complexity of embedded software means in-field upgrades are becoming unavoidable. Instead of dismissing this trend as a development issue, manufacturers like Microchip are addressing the need head- on, by introducing innovative solutions to in-field software upgrades. The PIC32MZ integrates Dual-Panel
Flash memory that allows a full software update to take place while the device is in service, executing program code at full speed. It achieves this by dividing the embedded Flash in to two physical and logical blocks, or panels. Each panel has its own charge pump and programming circuit, which means one panel is effectively ghost memory right up to the point when it becomes the main memory. As both panels essentially operate
independently, one panel continues to operate at full speed while the other is updated in the background, without interrupting program execution. Once the software update is installed and validated, the device can be reset and start executing memory from the newly programmed panel. The use of a microAptiv core features
an MMU (Memory Management Unit) and instruction and data caches, and up to 2048KB of on chip flash with up to 512kbyte of SRAM, capable of supporting multiple protocol stacks running simultaneously, as well as buffer space to support audio processing, and frame buffers to support displays up to WQVGA resolution, all without the need for an external graphics chip.
Microchip
www.microchip.com O118 921 5800
Enter 227 ELECTRONICS | MAY 2014 21
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