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Integration HPC 2012 Behind the scenes


The different sides of integration in high-performance computing The future lies with 3D integration, says IEEE Technical Expert, Professor Steve Furber


In order to make exascale machines viable, we have to bring the energy efficiency of HPC up by a couple of orders of magnitude. Tey


have to be significantly more energy efficient than the best mobile phones we have today, while still achieving the same levels of performance. Nobody’s sure if it’s possible, but the kind of technology that is going to have to be involved in reaching this target is 3D integration. 3D integration means bringing the


memory subsystems closer to the processors. Te general pattern I expect to see here is


a many core processor chip packaged with layers of memory connected through 3D integration technology, which will mean through silicon vias. Tis technology is already out there and available, but is not actually able to be manufactured in high reliability and volumes, as far as I’m aware. Getting the memory so close to the processor means that the memory can be accessed with much lower energy costs, but this is only part of the solution. Te problem with going to 3D integration


is that we are packaging several sources of heat into the same physical package and so have to reduce that heat generation in order


“Getting the memory so close to the processor means that the memory can be accessed with much lower energy costs”


to make the technology feasible. At the moment, high-end processors are running at tens of Watts. Te current leading energy- efficiency technology in HPC is the IBM Blue Gene/Q and while these machines represent a significant step forward, they still use a processor chip with around 18 cores on it, which dissipates in the region of 55


Watts. Integrating something like that into a 3D package with memory would almost certainly put the power beyond what the package could handle. We have to do much better on the processor energy as well as the 3D packaging to drive down the total energy costs of the system.


David Power, head of HPC at Boston, offers predictions for HPC integration beyond 2012


In the future, we may still use racks, but we will design and integrate at the rack (and data centre) level. Instead of individual network ports with spaghetti wiring between servers, we’ll use a fabric interconnect to expose a single (or several) network ports for a whole rack (including built-in resiliency, high availability and fault tolerance through multi-path fabric connections). We will use System-on-Chip (SoC) technology to integrate all but the system RAM and (flash) storage onto the server chip – including all of the IO, offload, GPGPU, etc. –


Further information


Ace Computers www.acecomputer.com


Acer www.acer.com


Advanced Cluster Systems www.advancedcluster systems.com


Advanced Clustering Technologies www.advancedclustering.com


Amax Technologies www.amaxtech.com


Appro www.appro.com


Boston www.boston.co.uk


Bull www.bull.com/ extremecomputing


Cambridge Computer www.cambridgecomputer.com


Ciara Technologies www.ciaratech.com


Cluster Vision www.clustervision.com


Cray www.cray.com


Dell www.dell.com


E4 Computer Engineering www.e4company.com


Eurotech www.eurotech.com


Fujitsu www.fujitsu.com


HP www.hp.com


IBM www.ibm.com


IEEE www.ieee.org


Intel www.intel.com


Megware www.megware.com


Mircoway Inc www.microway.com


NEC www.nec.com


Partec www.par-tec.com


Pico Computing www.picocomputing.com


RSC www.rscgroup.ru


SGI www.sgi.com


Scalable Informatics www.scalableinformatics.com


Silicon Mechanics www.siliconmechanics.com


Supermicro www.supermicro.com


T-Platforms www.t-platforms.ru


Tyan Computer www.tyan.com


Workstation Specialists www.workstation specialist.com


and further down the line, Package-on-Package will allow us to integrate some (or all) of the rest. System-on-Chip technology, which began life as an embedded systems technology (but is primed to storm the data centre in the next few years), allows for mass levels of integration at high density. Combining this with ARM-based servers that require little active cooling, we will see up to 10,000 server nodes in a single rack. Performance in the Hyperscale world will


be gained in aggregate, at low energy, not necessarily through having a small number of


beefy and energy-inefficient servers. Although we will still see servers featuring dozens of fully coherent chips with elaborate interconnects and hundreds of cores, Hyperscale will be more about having thousands of individual servers, each having a smaller number of cores. Tis is consistent with the general trend in the industry away from single-core scalability. Everyone has given up on linear single core


growth as the strategy and it’s time to give up on a strategy of single-system coherent designs that are energy inefficient and complex to


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