40 nanotimes News in Brief

CNT Circuits // Stanford Engineers Perfecting Carbon Nanotubes for Highly Energy-Efficient Computing, © Based on Material by Andrew Myers / Stanford School of Engineering, USA

Engineers at Stanford have found ways around the challenges to produce the first full-wafer digital logic structures based on carbon nanotubes. Over the last few years, a team of Stanford engineering professors, doctoral students, undergraduates, and high-school interns, led by Professors Subhasish Mitra and H.-S. Philip Wong, took on the challenge and has produced a series of breakthroughs that represent the most advanced computing and storage elements yet created using CNTs. These high-quality, robust nanotube circuits are immune to the stubborn and crippling material flaws that have stumped researchers for over a decade, a difficult hurdle that has prevented the wider adoption of nanotube circuits in industry. The advance represents a major milestone toward Very-large Scale Integrated (VLSI) systems based on nanotubes. 

"The first CNTs wowed the research community with their exceptional electrical, thermal and mechanical properties over a decade ago, but this recent work at Stanford has provided the first glimpse of their viability to complement silicon CMOS transistors," said Larry Pileggi, Tanoto Professor of Electrical and Computer Engineering at Carnegie Mellon University and director of the Focus Center Research Program Center for Circuit and System Solutions.

The Stanford design approach has two striking features in that it sacrifices virtually none of CNTs’ energy efficiency and it is also compatible with existing fabrication methods and infrastructure, pushing the technology a significant step toward commercialization. "This transformative research is made all the more promising by the fact that it can co-exist with today’s mainstream silicon technologies, and leverage today’s manufacturing and system design infrastructure, providing the critical feature of economic viability," said Betsy Weitzman of the Focus Center Research Program at the Semiconductor Research Corporation The Stanford team’s work was featured recently as an invited paper at the prestigious International Electron Devices Meeting (IEDM) as well as a "keynote paper" in the prestigious IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

"Many researchers assumed that the way to live with imperfections in CNT manufacturing was through expensive fault-tolerance techniques. Through clever insights, Mitra and Wong have shown otherwise. Their inexpensive and practical methods can significantly improve CNT circuit robustness, and go a long way toward making CNT circuits viable," said Sachin S. Sapatnekar, Editor-in-Chief, IEEE Transactions on CAD. "I anticipate high reader interest in the paper," Sapatnekar noted.

Jie Zhang, Lin, A., Patil, N., Hai Wei, Lan Wei,  Wong, H.-S.P., Mitra, S.: Carbon Nanotube Robust Digital VLSI, In: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Volume 31, Issue: 4, April 2012, Pages 453-471, DOI:10.1109/TCAD.2012.2187527

 _{http://dx.doi.org/10.1109/TCAD.2012.2187527}