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HIGH PERFORMANCE COMPUTING


Tech focus: Processor diversity


ROBERT ROE TAKES A LOOK AT THE PROCESSING TECHNOLOGIES AVAILABLE TO HPC AND AI USERS


architecture has already stolen headlines from Intel over the last 12 months. Now that AMD has the second generation of its EPYC silicon - denoted as ‘Rome’ - it is expected to capture market share from Intel.


The Rome chips deliver impressive


With new technologies on the horizon and increasingly competitive products available to


the HPC community there is an increased choice in the HPC processor market. The majority of HPC systems still use Intel CPUs with an increasing use of acceleration technologies – normally supplied by Nvidia. However, there are now more realistic alternatives out there for HPC users who want to explore the use of new technologies. In the processor space, we now have


Intel, IBM, AMD and Arm all vying for HPC business. Tachyum also recently announced it had joined the Open Compute Project targetting datacentre, AI and HPC workloads. GPUs are also seeing increased


competition – with Intel, AMD and Nvidia all aiming to compete in this market for accelerated computing in HPC and AI/ ML. There are also increasing numbers of more specialised processor choices available for AI and ML applications from companies such as Graphcore. AMD is the most successful of the challengers today and has already demonstrated its competitiveness with the current generation of Intel technologies. AMD’s EPYC processor


4 Scientific Computing World February/March 2020


price performance, and this is likely to help fuel a surge of systems in both the US and Europe with some large contracts already announced at the end of 2019. For example, the DOE system Frontier will make use of AMD technologies; likewise, the UK’s Archer2 will be based on the Epyc processors.


Arm HPC development Arm and Fujitsu have spent more than the last five years developing its A64FX processor, which will be used in the upcoming RIKEN supercomputer. Arm has made improvements to its architecture from an HPC standpoint, the largest change being the Scalable Vector Extension (SVE). The co-development with Fujitsu is now starting to bear fruit, as the RIKEN Post K computer – which is reported to be in the region of 400 petaflops - will demonstrate the viability of this processor at scale. Toshiyuki Shimizu, senior director for the Platform Development Unit at Fujitsu,


‘The Arm architecture is one of the RISC architectures, and Fujitsu utilised our technologies obtained through our long CPU development history’


comments on the decision to select Arm to develop the processor technology for HPC: ‘The Arm instruction set architecture (ISA) is a well-maintained open standard which is accessible and usable by anyone. It also has a rich ecosystem for embedded, IoT and mobile systems.’ ‘The Armv8-A has suitable security


capabilities even for mission-critical applications. We, as a lead partner in this collaboration, enhanced the Arm architecture with the ISA extension, known as scalable vector extension (SVE), to optimise Arm for high-performance computing,’ stated Shimizu. ‘Arm developed the ISA extension


known as SVE, scalable vector extension, for high-performance servers. Fujitsu worked with Arm as a lead partner to develop it, the SVE has the capability to support 2048 bit SIMD and A64FX uses 512 bit. The SVE is also good for AI applications,’ Shimizu added. It is clear that this extension, while useful for HPC, is not only designed with Fugaku in mind but also future supercomputer development. The Previous RIKEN systems used the


RISC architecture, which has some shared history with the Arm processors we see today. As this is the closest available technology to the previous RISC based systems, the Fujitsu and RIKEN teams have expertise with the architecture. Shimizu added: ‘The Arm architecture is one of the RISC architectures, and Fujitsu utilised our technologies obtained through our long CPU development history. A64FX, the Fujitsu developed Arm CPU for the Fugaku supercomputer, is based on the microarchitecture of SPARC64 VIIIfx, K computer’s CPU. Memory bandwidth and calculation performance are balanced for application performance compatibility,


@scwmagazine | www.scientific-computing.com


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