Column: Silicon systems design
Beyond the accelerator: Verifying the new AI scale-up fabric
By Mike Bartley, CEO, Alpinum U
ALink and UCIe are bringing more of the verifi cation work into the connections between accelerators, chiplets and soſt ware.
T e task is to check that these parts continue to operate correctly when they are integrated and exercised as a system. Problems seen aſt er integration are
not always failures of an individual block. An accelerator may have passed its functional tests and the link may behave correctly against the protocol, yet the assembled platform can still fail when traffi c from several endpoints
is active. Shared credits and buff ers are one source of interaction. Reset state, management settings and soſt ware confi guration introduce others. T ese cases need to be exercised at the level where the components are actually connected. T at’s why the practical verifi cation
boundary for AI hardware is shiſt ing outward.
The accelerator is no longer the whole verification target UALink was created as an open scale-up interconnect for accelerator-to-accelerator communication. Its 200G 1.0 specifi cation targets connectivity for up to 1,024
accelerators within an AI computing pod. T e consortium’s 2026 specifi cation update added Common 2.0, separated the 200G data-link and physical-layer specifi cation, and introduced manageability and chiplet- specifi c specifi cations alongside in-network compute.
T e extra scale changes the conditions
that need to be tested. Verifi cation of one accelerator can concentrate on its local function. A fabric has to be run with multiple active endpoints, competing traffi c and pressure on shared resources. Recovery also needs to be checked while the rest of the system is still operating. For example, bringing one endpoint back aſt er a reset should not leave outstanding traffi c or shared state in an inconsistent condition. Protocol checks tell us whether an
interface behaves as specified. They do not cover every interaction created when several interfaces, endpoints and software-controlled functions are active at the same time.
10 November 2026
www.electronicsworld.co.uk
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