Feature: Aerospace, Military & Defence
determine if there is a process defectivity. A leakage test involves powering down the device and applying both positive and zero voltage to check for any current flow. If current is detected, it indicates a process defect, and those units should not undergo qualification stress. Subjecting them to stress might lead to a false failure, making it challenging to identify the root cause, which could be related to the fabrication process. However, incorporating hardware for a leakage test into the
final hardware interface board (HIB) can be complex. To address this, a probe card can be constructed to conduct the leakage test even before the die is assembled into the final package. Tis enables early identification of any process defects. Another common failure during qualification arises from
assembly issues. Tis can be attributed to factors such as Copper pillar on silicon or high pin-count BGA packages, which can reach up to 900 pins, sometimes leading to complications with under-bump metallurgy. One effective way to identify and address assembly issues is by implementing a continuity test, encompassing both positive and negative continuity testing. Tis enables the early detection of assembly problems, even before the functional and parametric tests are conducted. It also aids in pinpointing the source of the issue. In some cases, continuity testing is conducted at the die level using a probe card prior to the final package assembly. Tis practice not only reduces costs but also provides an estimate of final sample quantities, contributing to cost reduction and better planning for the team. It’s important to note that a continuity test indicates an
assembly-related issue, which is distinct from a device-related qualification failure. If a failure is related to the packaging process, it is considered a packaging-related issue in terms of qualification. However, if it’s an issue related to packaging, steps can be taken to rectify it. One common area for assembly issues is wire bonder misalignment, epoxy application and curing profile temperature. It has been observed that a significant portion of reliability failures over the years can be attributed to assembly- related issues. Terefore, implementing a robust approach to electronic packaging during assembly can significantly reduce qualification-related failures.
Figure 4: Typical lab setup for continuity testing of the integrated circuit Te direct current high temperature operating life (DCHTOL)
test is crucial for predicting device reliability over time. By stressing the device from 70°C to 125°C, we find an acceleration factor (AF) of about 118. Tis means that each hour of testing at 125°C is equivalent to roughly 118 hours of normal use at 70°C.
diodes
Figure 5: External clock of 125MHz going to each of the HTOL site for the internal clock within Apollo MxFE]
For 1,000 hours of DCHTOL stress, it translates to
approximately 13.58 years. Tis stress is especially critical for ADI’s Apollo MxFE AD9084, used in phased array radars and space applications, where devices are expected to operate for significant time periods.
Figure 3: Continuity testing usually involves testing of the ESD protection 34 May 2025
www.electronicsworld.co.uk
[INSERT Equation 1] During testing, issues like loading or heat sink problems can
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46
