Feature: Processors
Table 1: Comparison of energy per inference metric of a NASP chip vs some digital solution
the human visual nerve and retina, and a flexible part (which can differ depending on application), responsible for further classification of the received embeddings. Tere is a well-known phenomenon of
Machine Learning: aſter several hundred training cycles (also known as epochs), the deep convolutional neural network maintains fixed weights and the structure of the first 80-90% of the layers, and in the following cycles, only the few last layers responsible for classification continue to change weights – a property also used in Transfer Learning. Tis fact is key to a hybrid concept, where a chip with fixed neural networks is responsible for pattern detection, combined with a flexible algorithm – which could be any type, including an additional flexible neural network responsible for pattern interpretation. Te fundamental parts of the NASP
hybrid design therefore are: • A fixed neuromorphic analogue core, with ultra-low power and low latency when generating embeddings;
• A fully-flexible digital core, applied for final classification. See Figure 2 for a neural network
implementation with Transfer Learning technique in a digital standard node vs the NASP hybrid solution that uses an analogue circuit. Te neural network (NN) running on
digital processors (CPU, GPU and TPU) allocates resources in the following way: 1. Raw data pre-processing consumes about 80% of the computational resources; 2. Classification and decision making consume much fewer resources. Te NASP solution uses the principle of
Transfer Learning, where the most layers of a neural network responsible for raw data pre-processing remain unchanged aſter a certain number of training epochs (Fixed Analogue Core), and only the last few layers are updated while receiving new data
and retraining it (Flexible Digital Core). Another important element of the NASP
solution is effective pruning to minimise the trained network, which is to be converted into chip production files. Since the neural core runs with weights, fixed aſter training of the neural network, we can effectively prune the initial neural network before converting it into an internal math model in a digital format. Pruning can reduce the neural network between two and 50 times, depending on its structure. And since the final chip is built according to the prepared architecture and structure, pruning drastically reduces the final chip size and power consumption.
NASP performance Table 1 shows a comparison of energy per inference metric of a NASP chip vs some digital solutions. Raspberry Pi3 B+ has one processor,
Snapdragon has a processor with a GPU accelerator, and Nvidia Jetson has a 256- core GPU. For NASP, we have used a chip simulation (D-MVP) model and data from the NASP test chip. Te comparison demonstrates NASP’s
greater energy efficiency, due to the analogue neuromorphic nature of the IC. Also, it is important that the NASP chip size completely fits the requirements of the neural network (Mobile Net v2), leaving no overhead at all. Tis is especially important for small neural networks, where the NASP efficiency advantage becomes much greater.
Examples of NASP use Te embedding extraction and processing approach in human activity recognition is based on three-axis accelerometer signals. A trained autoencoder neural network encodes various types of human activities, and then decodes them without losing accuracy. Aſter generating such an array of
patterns (embeddings), a neural network
will recognise the human activities encoded in the patterns. Te system consists of an encoder function, implemented in fixed neurons in an analogue processor (NASP), and the classifier, implemented in a digital processor. The fixed analogue part of the NASP chip takes approximately 90% of the whole workload, and the activity recognition interpretation takes around 1%, resulting in a low load on the digital subsystem. An important feature of using such
embeddings generated by the encoder neural network is that, if a human practiced some new physical activity (which was not trained previously during the neural network training stage), the unique descriptor would be formed anyway, differentiating this activity from other classes of embeddings. Tus, it would be a totally new compact size pattern dedicated to that activity. In other words, it is still possible to introduce new classes not included in the fixed trained network, significantly broadening the application of NASP-based products. Taking this to the industrial setting,
predictive maintenance helps optimise processes by collecting and analysing the huge data flow generated by vibrational sensors that measure machinery, tracks, railway cars, wind turbines and oil and gas pumps. Tis data flow shortens the battery life of operating sensor nodes. A NASP solution reduces the data flow from vibration sensors by 1000 times, using the same encoder-decoder approach and transmitting through LoRa (or other low-power technology) only embeddings extracted from the initial data. It is worth noting that the autoencoder systems and embedding will create new classes, describing new signals of vibration sensors, even if they were not trained to recognise these types of signal patterns. Tus, by applying an encoder neural network, in this case rigidly built in NASP, a whole range of different signals from various vibration sensors can be obtained for analysis by a digital system, which will identify any machine malfunction. Use of the embeddings reduces data sent to the cloud, solving the fundamental problem of low bandwidth required by IoT systems.
www.electronicsworld.co.uk July/August 2022 21
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