DISPLAYS & UIs
JEIDA standard. MIPI DSI on the other hand can transmit not only video/image data but also command signals. Both signals can be controlled in accordance with the specific handshake sequence and rules.
Bridge between DSI and LVDS If the application process doesn’t support a standard or does not have enough lanes to connect to a display module, a bridge IC can create the corresponding interface between the video output of the processor and the input of the display module, the camera or other peripheral devices. This allows application processes to be connected to various displays without having to re- develop the entire system. Toshiba offers a range of these bridge ICs.
Figure 2: An FPD System with Four LVDS Pairs
displays and the application processor. They define a serial bus and a communication protocol for data transfer between the host, the image data source, and the target application. They were developed to enable lower-cost display controllers for mobile devices such as smartphones, laptops and tablet PCs, wearables, augmented reality applications and vehicle instrument panels.
The physical layer MIPI-DSI is based on the physical layer MIPI D- PHY. It is used to connect megapixel cameras and high-resolution displays with an application processor. A clock-forwarding, synchronous link is used here that combines high-speed data transmission with low power consumption as well as high resistance to interference and high jitter tolerance with low costs (Figure 3). At the physical layer, DSI specifies a serial
point-to-point high-speed differential signal bus. It encompasses a high-speed clock lane and one or several data lanes. Each lane covers two wires due to the differential signal use. All lanes run from the DSI host to the DSI device with the exception of the first data lane (Lane 0). It is capable of a bus turnaround operation (BTA) that allows the direction of transmission to be reversed. When several lanes are used, they transmit data in parallel, thus allowing four bits to be transmitted simultaneously when four lanes are being used. The connection operates either in low-
power mode or high-speed mode. The transition between the two modes is done with minimal latency. In low-power mode, the maximum speed clock is disabled and the signal clock information is embedded in the data. The data rate is not enough to control a display, but can be used to send configuration information and commands. In high-speed mode the high-speed clock is used at frequencies of several tens of
Megahertz up to over a Gigahertz as a bit clock for the data lanes. The clock speeds vary depending on the requirements of the display. Because only a low voltage is required for the signal output and the data is transmitted in parallel, high-speed mode can operate with minimal power usage.
Further DSI layers In terms of lane management, the transmitter distributes the transmitted data over one or several of the four lanes, depending on bandwidth requirements. For mapping – the method of determining which bit is transmitted over which lane – the standards from VESA (Video Electronics Standards Association) and JEIDA (Japan Electronic Industry Development Association) are well established. The low-level protocol layer defines how the
bits and bytes are organised into packets and which bits constitute the header and payload. This is also where error-checking is performed. At the application level, data from the layer beneath is finally translated into pixels or commands.
LVDS vs. MIPI DSI A comparison of LVDS and MIPI DSI reveals only one common factor: both use four lanes. LVDS only transmits the video/image signal though, for which the RGB-TTL signal is converted into an LVDS signal using the SPWG (Standard Panels Working Group) or
They are suitable for consumer, industrial and automotive applications such as smartwatches, tablet PCs, ultrabooks, 4K UHD displays, smart TVs, wearables, cameras, gaming accessories, head-mounted displays (HDMs), LCDs, IO port expansions or POS applications. The DSI-LVDS bridge enables ICs to control
an LVDS-compatible display via a DSI link. These support a pixel resolution of 24 bits. The TC358771XBG and TC358774XBG models enable classic 4:3 (UXGA, Ultra Extended Graphics Array) with a resolution of 1600 × 1200 pixels over DSI Single Link. The TC358772XBG and TC358775XBG models support WUXGA (Wide Ultra eXtended Graphics Array), which enables displays with 16:10 format and a resolution of 1920 × 1200 pixels over DSI Dual Link. The bridge ICs also support an I2C master controlled by the DSI link that can be used as an interface with other control functions via I2
C. The bridge ICs operate using the LVDS
standard at 135MHz, while in the DSI standard they transmit at up to 1Gbit/s per lane. They support the video input formats RGB565/666/888. By optimising the backlighting of LCD displays based on ambient light, they help to reduce the power usage of mobile devices. Using bridge ICs such as those from
Toshiba, developers can also leverage the advantages of DSI – low power usage, pixel data rates and component costs – for designs that do not support DSI, providing them with the flexibility they need in such a rapidly developing market.
Rutronik
www.rutronik.com
Figure 3: The physical layer D-PHY connects the application process to the display. OCTOBER 2021 | ELECTRONICS TODAY 29
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