TEST & MEASUREMENT Proven by design: Why design for test defines reliable ASIC development
Electronic systems are being asked to do more than ever before, often operating continuously in demanding environments where performance, safety and longevity are all critical requirements. As products become more complex and expectations of reliability continue to rise, manufacturers must ensure quality is built into a design from the very beginning, rather than verified only at the end of development.
By Ross Turnbull, director of business development Swindon Silicon Systems I
n semiconductor test engineering, this is known as the ‘rule of ten’: the principle that the cost of finding a fault rises by roughly an order of magnitude with each stage it is missed, from design through to the field. What may be a straightforward correction during development can become a costly manufacturing issue or even lead to product failure once deployed. For ASICs, designing for testability from the outset helps manufacturers detect faults earlier, improve production efficiency and reduce the risk of failures reaching end users.
Where reliability actually starts Design for test (DFT) is the practice of building testability into a chip’s architecture from the outset, rather than working out how to test it once the layout is already fixed. In an ASIC, this typically means adding structures such as scan chains, built-in self- test and boundary scan alongside the core logic, so internal nodes can be observed and controlled during production test. Left until late in the design cycle, testability becomes a compromise. Engineers are forced to work around a layout that was never intended to be tested, often accepting lower fault coverage or adding external test hardware to make up the difference. Considered early, the same structures can be planned in alongside the functional design, giving test engineers direct access to internal nodes during production testing. This matters because defects introduced during wafer fabrication are not always immediately apparent. A short, an open circuit or a timing fault may not show up as an obvious functional failure, but it can still cause a device to behave unpredictably
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once it reaches the field. Good DFT gives production test the visibility it needs to catch these faults before a chip is packaged, tested and shipped, rather than after.
From simulation to silicon Once a design reaches production, responsibility passes to wafer probe and automated test equipment (ATE), which screen every device against its specification before it leaves the factory. This is where the value of early DFT planning becomes concrete. Test programmes built around well-structured scan chains and self-test logic are quicker to develop, run faster on the tester and achieve higher fault coverage for the same test time.
The reverse is also true. A design with limited test access can require longer, more complex test programmes to reach an acceptable level of confidence, adding cost and time to every unit that passes through the line. At volume, that difference can compound quickly, affecting both the cost of the chip and how fast a manufacturer can turn wafers into shipped product. Early design decisions have a direct bearing on yield. The choices that determine what a design can ultimately achieve, and how efficiently that can be verified on the test floor, are made before production, at the architecture stage.
Working as one team
The strongest results tend to come from design and test engineering working on the same programme, rather than handing a finished design over the wall. A full turnkey approach, of the kind Swindon Silicon applies across its ASIC programmes, brings
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design, physical layout and production test under one roof, so test requirements can shape the design as it develops. This close collaboration delivers three explicit benefits: a faster feedback loop between design and test data, improved optimisation of test coverage against cost, area and power and a reduced risk of an undetected fault reaching the field. Test data from early silicon can be fed back to the design team quickly, and questions about coverage, test time or cost can be resolved before they become fixed limitations of the product. Without this level of integration, test requirements may be identified later in the development cycle, when opportunities to optimise the design are more limited. This can result in longer test development programmes, increased production costs and a greater risk of faults progressing further through manufacturing before they are detected.
For long-life applications in industrial, automotive and aerospace markets, where a field failure can mean a costly recall or years of diagnostic work, that reduced risk is often worth more than any saving made by treating test as an afterthought.
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