Data acquisition


not equal, any imbalance in output amplitude or phase produces an undesirable common-mode component in the output, which is amplified by its noise gain and causes a redundant noise and offset in the differential output of the FDA. Therefore, it is imperative that the ratio of gain/feedback resistors matches well. In other words, the combination of input source impedance and RG2 (RG1) should match (that is, β1 = β2) to avoid the signal distortion, mismatch in the common- mode voltage of each output signal, and prevent the increase in common-mode noise coming from the FDA. One of the ways to counter-balance differential offset and avoid output distortion is to add an external resistor in series with a gain resistor (RG1). Not only that, the gain error drift is also influenced by a choice of resistor type such as a thin film, low temperature coefficient resistor, while sourcing matched resistors is challenging amid cost and board space constraints. In addition, the generation of odd, bipolar


supplies is inconvenient for many designers due to the extra cost and real estate constraints on their PCBs. Designers also need to carefully select the optimal passive components, including an RC low- pass filter (which is placed between the ADC driver output and the ADC inputs) as well as decoupling capacitor for the successive approximation register (SAR) ADC dynamic reference node. An RC filter helps limit the noise at the ADC inputs and reduces the effect of kickbacks coming from the capacitive DAC input of a SAR ADC. The C0G or NP0 type capacitors and reasonable value of series resistance should be chosen to keep the amplifier stable and limit its output current. Finally, the PCB layout is extremely critical for preserving signal integrity and achieving the expected performance from the signal chain.


Easing thE CustomEr’s DEsign JournEy Many system designers end up implementing different signal chain architecture for the same applications. However, one size does not fit all, so Analog Devices, Inc. (ADI) has focused on common sections of signal chain, signal conditioning, and digitisation by providing more complete signal chain µModule solutions with advanced performance that bridge a gap between standard discrete components and highly integrated customer specific ICs to solve their major pain points. The ADAQ4003 is a SiP solution that provides the best balance between R&D cost and form factor reduction while accelerating time to prototypes. The ADAQ4003 µModule precision data


acquisition solution incorporates multiple common signal processing and conditioning blocks as well as critical passive components laid out into a single device using ADI’s advanced SiP technology (see Figure 5). The ADAQ4003 includes low noise, an FDA, a stable reference buffer, and a high resolution 18-bit, 2 MSPS SAR ADC. The ADAQ4003 simplifies the signal chain design and the development cycle of a precision measurement system by transferring component selection, optimisation, and layout from the designer to the device itself and solves all major


Instrumentation Monthly May 2021


Figure 3. Size comparison of the ADAQ4003 µModule device vs. a discrete signal chain solution.


issues discussed in the previous section. The precision resistor array around the FDA is built using ADI’s proprietary iPassives technology, which takes care of circuit imbalance, reduces parasitics, helps achieve superior gain matching up to 0.005 per cent, and has optimised drift performance (1 ppm/°C). The iPassives technology also offers a size advantage compared with discrete passives, which minimises temperature dependent error sources and reduces the system-level calibration burden. The fast settling and wide common-mode input range of the FDA, along with precision performance for configurable gain options (0.45, 0.52, 0.9, 1, or 1.9), allow gain or attenuation adjustments as well as fully differential or single- ended-to-differential input. The ADAQ4003 includes a single-pole RC filter


between the ADC driver and the ADC, which has been designed to maximise settling time and input


signal bandwidth. All the necessary decoupling capacitors for the voltage reference node and power supplies are also included to simplify bill of materials (BOM). The ADAQ4003 also houses a reference buffer configured in unity gain to optimally drive the dynamic input impedance of the SAR ADC reference node and the corresponding decoupling capacitor. A 10 µF on the REF pin is a critical requirement to help replenish the charge of an internal capacitive DAC during the bit decision process and vital to achieving peak conversion performance. With the inclusion of the reference buffer, the user can implement a much lower power reference source than many traditional SAR ADC-based signal chains because the reference source drives a high impedance node instead of the dynamic load of the SAR capacitor array. The user has the flexibility to choose the reference buffer input voltage that matches the desired analog input range.


small Form FaCtor EasEs PCB layout anD EnaBlEs high ChannEl DEnsity The 7 mm × 7 mm BGA package of the ADAQ4003 offers at least a four times footprint reduction compared to a traditional discrete signal chain (as shown in Figure 3), enabling small form factor instruments without sacrificing performance. The printed circuit board layout is critical for


preserving signal integrity and achieving the expected performance from the signal chain. The pinout of the ADAQ4003 eases the layout and allows its analogue signals on the left side and its digital signals on the right side. In other words, this allows the designers to keep the sensitive analogue and digital sections separate and confined to certain areas of the board and avoid crossover of digital and analog signals to mitigate radiating noise. The ADAQ4003 incorporates all


Figure 4. An ADAQ4003 FFT with shorted inputs, with the performance unchanged before and after removing the external decoupling capacitors for various rails.


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