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One of the big advantages with CoaXPress
is that it uses relatively cheap coaxial cabling that can reach distances of several tens of metres. Colin Pearce, CEO of Active Silicon, which is one of the founding members of the CoaXPress committee, commented that the main focus of CoaXPress is ‘high speed and “long” (in machine vision terms) cable lengths. ‘One of the aims of CoaXPress is always to
be able to support the fastest cameras on the market,’ added Pearce. ‘Longer cable lengths, i.e. 10 metres or more is opening up more machine vision applications without having to resort to costly and inconvenient extenders.’ In its current version, each CoaXPress
connection runs at up to 6.25 Gb/s, although Pearce said the intention is to move to 10 Gb/s and then to 12.5 Gb/s. EqcoLogic, now owned by Microchip Corporation and which manufactures the chips for CoaXPress, already has prototypes running at 10 Gb/s. Tese types of speed will be available in Version 2 of the standard, planned for release in mid-2015. Version 1.2, which is due at the end of 2014,
will support correction of single-bit errors, GenICam events to allow the camera to send information to the frame grabber, for example, and asynchronous serial communication to have a wider market appeal. Other important factors for machine
vision designed into CoaXPress from the start are GenICam support, real-time triggering (CoaXPress achieves near-real-time performance) and simple cabling through the use of coax with integral bi-directional communication and power. Camera Link HS (CLHS) is the other
interface designed for high-speed applications and is intended as a successor to Camera Link. CLHS has an 8b/10b implementation (M protocol) supporting a bit rate of 3.125 Gb/s per lane (although this is increasing to 5.0 Gb/s per lane over seven lanes), and a 64/66 encoding implementation at 10.3 Gb/s (X protocol). Te standard will migrate to higher speeds with transport layer technology improvements, according to Michael Miethig, R&D camera development manager at Teledyne Dalsa and chair of the CLHS committee. Te other advantage of CLHS is its low
latency and jitter for real time messages such as trigger and General Purpose Input/Output – 6.4ns jitter with 150ns latency. ‘Tese critical messages are single bit error tolerant to ensure reliable operation on the factory floor,’ Miethig stated. Tere is also a planned capability for
multiple regions of interest, enabling each ROI to have its own pixel type and bit depth.
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