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UltraScale drives the next generation of smarter systems
A look at how a new system architecture from Xilinix is proving interconnect technology is a vital key for the next generation of smarter systems
new generation of smarter systems is emerging with new high-performance architectural requirements. These include 400G OTN with intelligent packet processing and traffic management, 4 by 4 Mixed Mode LTE and WCDMA Radio with smart beam forming, 4K2K and 8K displays with smart image enhancement and recognition as well as the highest performance intelligence surveillance and reconnaissance systems (ISR) and other high performance computing applications for the data center. To implement such systems, address- ing the limitations to scalability of total system throughput and latency is no longer enough. Next generation silicon also needs to address interconnect - the number one bottleneck to system performance at advanced nodes. With the taping-out of one of the industry’s first 20nm UltraScale devices, Xilinx has proven itself equal to this challenge. The company advises it is giving customers a 1.5-2 times improvement in system-level perform- ance and programmable systems integration a year ahead of the compe- tition. The announcement means that the company has achieved two industry firsts: the taping out of one of the semi- conductor industry’s first 20nm devices (and one of the PLD industry’s first 20nm All Programmable device) and the implementation of the one of the industry’s first ASIC-class programmable architectures, UltraScale.
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These milestones follow a series of industry firsts from the company, which include one of the first 28nm tape-out, All Programmable SoCs, All Programmable 3D ICs, and SoC- strength design suite.
A new generation of systems Giles Peckham, European Marketing Director at Xilinx said: “This announcement is evidence of Xilinx’s continuing commitment to lead the industry and directly address the chal- lenges that our customers face in bringing next generation systems to market. We are getting to the 20nm process node first, and implementing
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our UltraScale architecture in silicon for the first time. Tuned to provide massive routing capacity and co-opti- mised with the Vivado design tools, this architecture delivers great levels of utilisation- more than 90 percent without degradation in performance.”
TSMC partnership
Xilinx has worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process, just as it had done in the development of 28HPL. The 28nm collaboration resulted in one of the industry’s first 28nm tape-out and an industry first in All Programmable FPGAs, SoC, and 3D IC devices, putting Xilinx a generation ahead in price/per- formance/watt, programmable systems integration, and BOM cost reduction. The company has now extended this formula from 28nm to 20nm, resulting in the one of the industry’s first tape-outs. The initial UltraScale devices will extend the company’s Virtex and Kintex FPGA and 3D IC families now based on 28nm process technology, and will serve as the foun- dation for future Zynq UltraScale All Programmable SoCs.
This architecture scales from 20nm planar through 16nm FinFET technolo- gies and beyond, while also scaling from monolithic through 3D ICs.
“Xilinx has worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process, just as it had done in the development of 28HPL. The 28nm collaboration resulted in one of the industry’s first 28nm tape-out and an industry first in All Programmable FPGA, SoC, and 3D IC devices”
UltraScale delivers the architecture required to manage multi-hundred giga- bit-per-second levels of system perform- ance with smart processing at full line
rate, scaling to terabits and teraflops. It does much more than simply increase the performance of each transistor or system block, or scale the number of blocks in the system. It fundamentally improves the communication, clocking, critical paths, and interconnect to address the massive data flow and intelligent packet, DSP, or image processing for the industry’s next gener- ation high performance applications mentioned above. UltraScale addresses these chal- lenges by applying ASIC techniques in a fully programmable architecture. For example, to address the challenges of massive data flow, it attacks the under- lying issues associated with clock skew, routing massive busses and managing system power at the extreme rates of next generation systems. With the use of multiregion ASIC-like clocking, designers can now place system-level clocks at the most optimal location - virtually anywhere on the die - leading to a reduction in system-level clock skew by as much 50 percent.
Figure 1: Xilinx’s
UltraScale SoC
The next-generation interconnect architecture, co-optimised with the Vivado Design Suite, is described by the company as a breakthrough in pro- grammable-logic routing. This routing architecture essentially removes routing congestion completely. The result is simple: if the design fits, it routes. This architecture offers significant system-level power reduction with each successive generation of All Programmable logic families. Low- power semiconductor processing coupled with significant static- and dynamic-power gating enabled through silicon and software techniques results in up to 50 percent overall system power savings over the company’s 7 series FPGA family. Moshe Gavrielov, Xilinx CEO concluded: “With the industry’s first 20nm tape-out,
first ASIC-class
UltraScale architecture, the first SoC- strength Vivado Design Suite, and con- tinuously expanding IP, C, and ARM processor-based solutions for smarter systems, Xilinx is once again expanding the value and market reach of the PLD industry. We are also bringing an extra generation of value to our customers a year ahead of the competition. Xilinx
www.xilinx.com Enter 201
NOVEMBER 2013 Electronics
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