FEATURE : PHOTONIC INTEGRATION
Analog Photonics demonstrated last year a reworkable 400G/fibre (100G/channel) SiP Engine that is scaling to 3.2Tb or more
needed. Te company intends to have a 3.2Tb chipset ready by the fourth quarter of next year. While many of the specifications are ready
for OBO and CPO products, Timurdogan highlighted the many current unknowns. He noted that CPO products will be harder to reach once installed, and may need to be pre-configured and sold together with CPO transceivers. ‘Tis makes the business model blurry, requiring switch maker, CPO transceiver and box companies to work closer than before.’
Good combination Intel Corporation’s Robert Blum agrees that 100Gb/s channels are likely to be part of co-packaged optics systems, but anticipates them being combined with 50TbE or 100TbE switches starting in late 2023 or 2024. ‘Tat’s where you can realise the benefits,’ he said. ‘When we did the analysis, we see about 30 per cent lower electrical power for the combined switch, and also similar improvements in cost.’ Intel’s journey to this stage starts with 1.6Tb/s
silicon PIC engines it has developed. ‘We have hybrid lasers that are part InP, part silicon, and we use InP photodiodes,’ Blum said. ‘On the pluggable modules today, we use different modulators that are much larger. For the photonic engine, we made ring modulators that are much smaller and integrated everything onto a single chip.’ On the packaging side, it’s another big
development to put a photonic engine with the driver chips, the TIA and the receivers. Ten, in March, the firm demonstrated a fully-functional 12.8Tb/s Ethernet switch based on CPO passing live traffic, exploiting four of its 1.6Tb/s engines. ‘You have the switch ASIC and you have to put the photonics around the entire chip because the I/O is so dense,’ Blum explained. Tis demonstration is a ‘stepping stone’, he
continued. ‘Te data rates that we would likely use for switches at 50TbE will be higher, using
10 FiBRE SYSTEMS n Issue 30 n Winter 2021
a 3.2Tb/s or 6.4Tb/s PIC, scaling that to the next switch.’ Aſter Intel atains that performance level it will ask the rest of the industry for commitments from hyperscale data centres to deploy these switches. ‘Tat’s an ask for the entire ecosystem to make that happen,’ Blum admited. ‘It’s not something that Intel or any other company would do in isolation.’ Blum also wants agreement on format standards. ‘To communicate between your photonic chip and the switch ASIC, you need some kind of short- reach Serdes’ he said. ‘What do you put on the photonics? What do you put in a switch ASIC? Tat needs to be aligned across the industry.’
Chicken and egg Andrew Rickman, CEO of Oxford-based silicon photonics firm Rockley Photonics echoed this outlook. ‘Tere is a chicken-and-egg problem,’ he said. ‘Production deployment of CPO needs substantial investment in technology and field trials, but this requires some form of financial commitment from the end-users.’ Tere is a clear need for agreement across the industry on numerous factors, he added. Tese include the interfaces between the ASIC and the optics, packaging and form factors of the CPO assembly, the engines, the external laser source and on the format of the overall supply chain. In 2020, Rockley demonstrated a 25.6Tb/s
OptoASIC switch. Its OptoASIC devices combine one or more PICs and ICs within a single package, such as a switch ASIC and the surrounding optics. Tey use OptoEngines to convert between optical and electrical signals for eight duplex channels each, a figure that is likely to be more when commercialised. ‘Internally, the OptoEngine comprises a transmit PIC, receive PIC, and corresponding transmit and receive ICs required to interface the main ASIC’s Serdes channels with the PICs,’ said Rickman. ‘Te transmit PIC incorporates modulators to imprint the electrical signal on
THIS MIGRATION HAS IMPORTANT RAMIFICATIONS FOR BOTH VENDORS AND USERS OF DATA CENTRE OPTICS
the outgoing optical signal. Optical power may be provided by lasers either integrated directly on the PIC, or coupled in from an external laser source. Te receiver PIC incorporates photodetectors to convert the incoming optical signal back to the electrical domain.’ CPO will also benefit users of high-
performance computing systems and specialised systems for machine learning, AI or big data processing, Rickman observed. ‘Generally, any use case where bandwidth is geting constrained by power, density, or cost can benefit from CPO,’ he said. Te fact that silicon-photonics-based
integration can enable high-volume OBO and CPO products reflects the supply chain’s maturity, Rickman added. Tat’s thanks to silicon photonics’ key advantage of using volume manufacturing to drive down cost. However he emphasised again that adoption is the main hurdle. ‘CPO needs to overcome substantial inertia to move an entire industry away from the entrenched model of pluggable optics,’ Rickman said. ‘Tis migration has important ramifications for vendors and users of data centre optics.’ n
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Analog Photonics
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